From: Catalin Marinas <catalin.marinas@arm.com>
To: Steven Price <steven.price@arm.com>
Cc: Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu
Subject: Re: [RFC PATCH 2/2] arm64: kvm: Introduce MTE VCPU feature
Date: Wed, 17 Jun 2020 15:38:10 +0100 [thread overview]
Message-ID: <20200617143809.GF5388@gaia> (raw)
In-Reply-To: <20200617123844.29960-3-steven.price@arm.com>
On Wed, Jun 17, 2020 at 01:38:44PM +0100, Steven Price wrote:
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index e3b9ee268823..040a7fffaa93 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -1783,6 +1783,17 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
> vma_pagesize = PMD_SIZE;
> }
>
> + if (system_supports_mte() && kvm->arch.vcpu_has_mte) {
> + /*
> + * VM will be able to see the page's tags, so we must ensure
> + * they have been initialised.
> + */
> + struct page *page = pfn_to_page(pfn);
> +
> + if (!test_and_set_bit(PG_mte_tagged, &page->flags))
> + mte_clear_page_tags(page_address(page), page_size(page));
> + }
Are all the guest pages always mapped via a Stage 2 fault? It may be
better if we did that via kvm_set_spte_hva().
--
Catalin
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kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Steven Price <steven.price@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
James Morse <james.morse@arm.com>,
linux-arm-kernel@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: Re: [RFC PATCH 2/2] arm64: kvm: Introduce MTE VCPU feature
Date: Wed, 17 Jun 2020 15:38:10 +0100 [thread overview]
Message-ID: <20200617143809.GF5388@gaia> (raw)
In-Reply-To: <20200617123844.29960-3-steven.price@arm.com>
On Wed, Jun 17, 2020 at 01:38:44PM +0100, Steven Price wrote:
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index e3b9ee268823..040a7fffaa93 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -1783,6 +1783,17 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
> vma_pagesize = PMD_SIZE;
> }
>
> + if (system_supports_mte() && kvm->arch.vcpu_has_mte) {
> + /*
> + * VM will be able to see the page's tags, so we must ensure
> + * they have been initialised.
> + */
> + struct page *page = pfn_to_page(pfn);
> +
> + if (!test_and_set_bit(PG_mte_tagged, &page->flags))
> + mte_clear_page_tags(page_address(page), page_size(page));
> + }
Are all the guest pages always mapped via a Stage 2 fault? It may be
better if we did that via kvm_set_spte_hva().
--
Catalin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Steven Price <steven.price@arm.com>
Cc: Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Dave Martin <Dave.Martin@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [RFC PATCH 2/2] arm64: kvm: Introduce MTE VCPU feature
Date: Wed, 17 Jun 2020 15:38:10 +0100 [thread overview]
Message-ID: <20200617143809.GF5388@gaia> (raw)
In-Reply-To: <20200617123844.29960-3-steven.price@arm.com>
On Wed, Jun 17, 2020 at 01:38:44PM +0100, Steven Price wrote:
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index e3b9ee268823..040a7fffaa93 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -1783,6 +1783,17 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
> vma_pagesize = PMD_SIZE;
> }
>
> + if (system_supports_mte() && kvm->arch.vcpu_has_mte) {
> + /*
> + * VM will be able to see the page's tags, so we must ensure
> + * they have been initialised.
> + */
> + struct page *page = pfn_to_page(pfn);
> +
> + if (!test_and_set_bit(PG_mte_tagged, &page->flags))
> + mte_clear_page_tags(page_address(page), page_size(page));
> + }
Are all the guest pages always mapped via a Stage 2 fault? It may be
better if we did that via kvm_set_spte_hva().
--
Catalin
next prev parent reply other threads:[~2020-06-17 14:38 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-17 12:38 [RFC PATCH 0/2] MTE support for KVM guest Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 12:38 ` [RFC PATCH 1/2] arm64: kvm: Save/restore MTE registers Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 14:05 ` Catalin Marinas
2020-06-17 14:05 ` Catalin Marinas
2020-06-17 14:05 ` Catalin Marinas
2020-06-18 10:43 ` Steven Price
2020-06-18 10:43 ` Steven Price
2020-06-18 10:43 ` Steven Price
2020-06-17 12:38 ` [RFC PATCH 2/2] arm64: kvm: Introduce MTE VCPU feature Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 12:38 ` Steven Price
2020-06-17 14:38 ` Catalin Marinas [this message]
2020-06-17 14:38 ` Catalin Marinas
2020-06-17 14:38 ` Catalin Marinas
2020-06-17 15:34 ` Steven Price
2020-06-17 15:34 ` Steven Price
2020-06-17 15:34 ` Steven Price
2020-06-26 16:40 ` James Morse
2020-06-26 16:40 ` James Morse
2020-06-26 16:40 ` James Morse
2020-06-23 17:48 ` [RFC PATCH 0/2] MTE support for KVM guest Catalin Marinas
2020-06-23 17:48 ` Catalin Marinas
2020-06-23 17:48 ` Catalin Marinas
2020-06-24 11:16 ` Steven Price
2020-06-24 11:16 ` Steven Price
2020-06-24 11:16 ` Steven Price
2020-06-24 14:21 ` Catalin Marinas
2020-06-24 14:21 ` Catalin Marinas
2020-06-24 14:21 ` Catalin Marinas
2020-06-24 14:59 ` Steven Price
2020-06-24 14:59 ` Steven Price
2020-06-24 14:59 ` Steven Price
2020-06-24 16:24 ` Catalin Marinas
2020-06-24 16:24 ` Catalin Marinas
2020-06-24 16:24 ` Catalin Marinas
2020-06-26 17:24 ` James Morse
2020-06-26 17:24 ` James Morse
2020-06-26 17:24 ` James Morse
2020-06-23 18:05 ` Peter Maydell
2020-06-23 18:05 ` Peter Maydell
2020-06-23 18:05 ` Peter Maydell
2020-06-24 9:38 ` Catalin Marinas
2020-06-24 9:38 ` Catalin Marinas
2020-06-24 9:38 ` Catalin Marinas
2020-06-24 10:34 ` Dave Martin
2020-06-24 10:34 ` Dave Martin
2020-06-24 10:34 ` Dave Martin
2020-06-24 11:03 ` Steven Price
2020-06-24 11:03 ` Steven Price
2020-06-24 11:03 ` Steven Price
2020-06-24 11:09 ` Catalin Marinas
2020-06-24 11:09 ` Catalin Marinas
2020-06-24 11:09 ` Catalin Marinas
2020-06-24 11:18 ` Steven Price
2020-06-24 11:18 ` Steven Price
2020-06-24 11:18 ` Steven Price
2020-06-24 11:52 ` Catalin Marinas
2020-06-24 11:52 ` Catalin Marinas
2020-06-24 11:52 ` Catalin Marinas
2020-06-24 13:16 ` Peter Maydell
2020-06-24 13:16 ` Peter Maydell
2020-06-24 13:16 ` Peter Maydell
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