From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, mperttunen@nvidia.com, bhuntsman@nvidia.com,
will@kernel.org, linux-kernel@vger.kernel.org,
praithatha@nvidia.com, talho@nvidia.com,
iommu@lists.linux-foundation.org, nicolinc@nvidia.com,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,
bbiswas@nvidia.com
Subject: Re: [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks
Date: Mon, 29 Jun 2020 15:38:34 -0700 [thread overview]
Message-ID: <20200629223833.GE27967@Asurada-Nvidia> (raw)
In-Reply-To: <20200629022838.29628-4-vdumpa@nvidia.com>
On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> +static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
> + struct arm_smmu_device *smmu,
> + int inst)
> +{
> + u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
> + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
> +
> + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
> + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
> + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
> + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
> +
> + if (!gfsr)
> + return IRQ_NONE;
Could move this before gfsynr readings to save some readl() for
!gfsr cases?
> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
[...]
> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
It reads FSR of the default inst (1st), but clears the FSR of
corresponding inst -- just want to make sure that this is okay
and intended.
> @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
> }
>
> nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
> - /* Free the arm_smmu_device struct allocated in arm-smmu.c.
> + /*
> + * Free the arm_smmu_device struct allocated in arm-smmu.c.
> * Once this function returns, arm-smmu.c would use arm_smmu_device
> * allocated as part of nvidia_smmu struct.
> */
Hmm, this coding style fix should be probably squashed into PATCH-1?
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org,
will-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
robin.murphy-5wv7dgnIgG8@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
yhsu-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
snikam-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
praithatha-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
talho-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
bbiswas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
nicolinc-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
bhuntsman-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Subject: Re: [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks
Date: Mon, 29 Jun 2020 15:38:34 -0700 [thread overview]
Message-ID: <20200629223833.GE27967@Asurada-Nvidia> (raw)
In-Reply-To: <20200629022838.29628-4-vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy <vdumpa-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> +static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
> + struct arm_smmu_device *smmu,
> + int inst)
> +{
> + u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
> + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
> +
> + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
> + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
> + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
> + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
> +
> + if (!gfsr)
> + return IRQ_NONE;
Could move this before gfsynr readings to save some readl() for
!gfsr cases?
> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
[...]
> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
It reads FSR of the default inst (1st), but clears the FSR of
corresponding inst -- just want to make sure that this is okay
and intended.
> @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
> }
>
> nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
> - /* Free the arm_smmu_device struct allocated in arm-smmu.c.
> + /*
> + * Free the arm_smmu_device struct allocated in arm-smmu.c.
> * Once this function returns, arm-smmu.c would use arm_smmu_device
> * allocated as part of nvidia_smmu struct.
> */
Hmm, this coding style fix should be probably squashed into PATCH-1?
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: snikam@nvidia.com, mperttunen@nvidia.com, bhuntsman@nvidia.com,
will@kernel.org, joro@8bytes.org, linux-kernel@vger.kernel.org,
praithatha@nvidia.com, talho@nvidia.com,
iommu@lists.linux-foundation.org, nicolinc@nvidia.com,
linux-tegra@vger.kernel.org, yhsu@nvidia.com, treding@nvidia.com,
robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,
bbiswas@nvidia.com
Subject: Re: [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks
Date: Mon, 29 Jun 2020 15:38:34 -0700 [thread overview]
Message-ID: <20200629223833.GE27967@Asurada-Nvidia> (raw)
In-Reply-To: <20200629022838.29628-4-vdumpa@nvidia.com>
On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> +static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
> + struct arm_smmu_device *smmu,
> + int inst)
> +{
> + u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
> + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
> +
> + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
> + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
> + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
> + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
> +
> + if (!gfsr)
> + return IRQ_NONE;
Could move this before gfsynr readings to save some readl() for
!gfsr cases?
> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
[...]
> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
It reads FSR of the default inst (1st), but clears the FSR of
corresponding inst -- just want to make sure that this is okay
and intended.
> @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
> }
>
> nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
> - /* Free the arm_smmu_device struct allocated in arm-smmu.c.
> + /*
> + * Free the arm_smmu_device struct allocated in arm-smmu.c.
> * Once this function returns, arm-smmu.c would use arm_smmu_device
> * allocated as part of nvidia_smmu struct.
> */
Hmm, this coding style fix should be probably squashed into PATCH-1?
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Krishna Reddy <vdumpa@nvidia.com>
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
linux-arm-kernel@lists.infradead.org,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
linux-tegra@vger.kernel.org, treding@nvidia.com, yhsu@nvidia.com,
snikam@nvidia.com, praithatha@nvidia.com, talho@nvidia.com,
bbiswas@nvidia.com, mperttunen@nvidia.com, nicolinc@nvidia.com,
bhuntsman@nvidia.com
Subject: Re: [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks
Date: Mon, 29 Jun 2020 15:38:34 -0700 [thread overview]
Message-ID: <20200629223833.GE27967@Asurada-Nvidia> (raw)
In-Reply-To: <20200629022838.29628-4-vdumpa@nvidia.com>
On Sun, Jun 28, 2020 at 07:28:38PM -0700, Krishna Reddy wrote:
> Add global/context fault hooks to allow NVIDIA SMMU implementation
> handle faults across multiple SMMUs.
>
> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
> +static irqreturn_t nvidia_smmu_global_fault_inst(int irq,
> + struct arm_smmu_device *smmu,
> + int inst)
> +{
> + u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
> + void __iomem *gr0_base = nvidia_smmu_page(smmu, inst, 0);
> +
> + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
> + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
> + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
> + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
> +
> + if (!gfsr)
> + return IRQ_NONE;
Could move this before gfsynr readings to save some readl() for
!gfsr cases?
> +static irqreturn_t nvidia_smmu_context_fault_bank(int irq,
> + void __iomem *cb_base = nvidia_smmu_page(smmu, inst, smmu->numpage + idx);
[...]
> + fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
[...]
> + writel_relaxed(fsr, cb_base + ARM_SMMU_CB_FSR);
It reads FSR of the default inst (1st), but clears the FSR of
corresponding inst -- just want to make sure that this is okay
and intended.
> @@ -185,7 +283,8 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
> }
>
> nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
> - /* Free the arm_smmu_device struct allocated in arm-smmu.c.
> + /*
> + * Free the arm_smmu_device struct allocated in arm-smmu.c.
> * Once this function returns, arm-smmu.c would use arm_smmu_device
> * allocated as part of nvidia_smmu struct.
> */
Hmm, this coding style fix should be probably squashed into PATCH-1?
next prev parent reply other threads:[~2020-06-29 22:39 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-29 2:28 [PATCH v7 0/3] Nvidia Arm SMMUv2 Implementation Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` [PATCH v7 1/3] iommu/arm-smmu: add NVIDIA implementation for dual ARM MMU-500 usage Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 21:51 ` Nicolin Chen
2020-06-29 21:51 ` Nicolin Chen
2020-06-29 21:51 ` Nicolin Chen
2020-06-29 21:51 ` Nicolin Chen
2020-06-29 22:49 ` Krishna Reddy
2020-06-29 22:49 ` Krishna Reddy
2020-06-29 22:49 ` Krishna Reddy
2020-06-29 22:49 ` Krishna Reddy
2020-06-29 23:52 ` Nicolin Chen
2020-06-29 23:52 ` Nicolin Chen
2020-06-29 23:52 ` Nicolin Chen
2020-06-30 10:23 ` Jon Hunter
2020-06-30 10:23 ` Jon Hunter
2020-06-30 10:23 ` Jon Hunter
2020-06-30 10:23 ` Jon Hunter
2020-06-30 10:46 ` Robin Murphy
2020-06-30 10:46 ` Robin Murphy
2020-06-30 10:46 ` Robin Murphy
2020-06-30 10:46 ` Robin Murphy
2020-06-29 2:28 ` [PATCH v7 2/3] dt-bindings: arm-smmu: Add binding for Tegra194 SMMU Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` [PATCH v7 3/3] iommu/arm-smmu: Add global/context fault implementation hooks Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 2:28 ` Krishna Reddy
2020-06-29 22:38 ` Nicolin Chen [this message]
2020-06-29 22:38 ` Nicolin Chen
2020-06-29 22:38 ` Nicolin Chen
2020-06-29 22:38 ` Nicolin Chen
2020-06-29 23:28 ` Krishna Reddy
2020-06-29 23:28 ` Krishna Reddy
2020-06-29 23:28 ` Krishna Reddy
2020-06-29 23:28 ` Krishna Reddy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200629223833.GE27967@Asurada-Nvidia \
--to=nicoleotsuka@gmail.com \
--cc=bbiswas@nvidia.com \
--cc=bhuntsman@nvidia.com \
--cc=iommu@lists.linux-foundation.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=mperttunen@nvidia.com \
--cc=nicolinc@nvidia.com \
--cc=praithatha@nvidia.com \
--cc=robin.murphy@arm.com \
--cc=snikam@nvidia.com \
--cc=talho@nvidia.com \
--cc=treding@nvidia.com \
--cc=vdumpa@nvidia.com \
--cc=will@kernel.org \
--cc=yhsu@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.