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From: lazyparser@gmail.com
To: qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com,
	Wei Wu <lazyparser@gmail.com>
Subject: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
Date: Tue,  7 Jul 2020 18:09:30 +0800	[thread overview]
Message-ID: <20200707100930.4041-1-lazyparser@gmail.com> (raw)

From: Wei Wu <lazyparser@gmail.com>

`imm20` operand type is used in LUI/AUIPC and other instructions.
The value should not be left shifted 12bits for disassembly output.

Signed-off-by: Wei Wu <lazyparser@gmail.com>
---
 disas/riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 278d9be924..a2b6472bd8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
 
 static int32_t operand_imm20(rv_inst inst)
 {
-    return (((int64_t)inst << 32) >> 44) << 12;
+    return ((int64_t)inst << 32) >> 44;
 }
 
 static int32_t operand_jimm20(rv_inst inst)
-- 
2.17.1



             reply	other threads:[~2020-07-07 14:37 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07 10:09 lazyparser [this message]
2020-07-07 15:15 ` [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand Alistair Francis
2020-07-07 15:47   ` Wei Wu (吴伟)
  -- strict thread matches above, loose matches on Subject: below --
2020-07-07 15:43 Wei Wu
2020-07-10 18:30 ` Richard Henderson
2020-07-07  8:20 Wei Wu (吴伟)

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