* [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
@ 2020-07-07 8:20 Wei Wu (吴伟)
0 siblings, 0 replies; 6+ messages in thread
From: Wei Wu (吴伟) @ 2020-07-07 8:20 UTC (permalink / raw)
To: qemu-riscv; +Cc: Palmer Dabbelt, Alistair Francis
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`imm20` operand type is used in LUI/AUIPC and other instructions.
The value should not be left shifted 12bits for disassembly output.
Signed-off-by: Wei Wu <lazyparser@gmail.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 278d9be924..a2b6472bd8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
static int32_t operand_imm20(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 44) << 12;
+ return ((int64_t)inst << 32) >> 44;
}
static int32_t operand_jimm20(rv_inst inst)
--
2.17.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
@ 2020-07-07 10:09 lazyparser
2020-07-07 15:15 ` Alistair Francis
0 siblings, 1 reply; 6+ messages in thread
From: lazyparser @ 2020-07-07 10:09 UTC (permalink / raw)
To: qemu-riscv; +Cc: palmer, Alistair.Francis, Wei Wu
From: Wei Wu <lazyparser@gmail.com>
`imm20` operand type is used in LUI/AUIPC and other instructions.
The value should not be left shifted 12bits for disassembly output.
Signed-off-by: Wei Wu <lazyparser@gmail.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 278d9be924..a2b6472bd8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
static int32_t operand_imm20(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 44) << 12;
+ return ((int64_t)inst << 32) >> 44;
}
static int32_t operand_jimm20(rv_inst inst)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
2020-07-07 10:09 [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand lazyparser
@ 2020-07-07 15:15 ` Alistair Francis
2020-07-07 15:47 ` Wei Wu (吴伟)
0 siblings, 1 reply; 6+ messages in thread
From: Alistair Francis @ 2020-07-07 15:15 UTC (permalink / raw)
To: lazyparser@gmail.com, qemu-riscv@nongnu.org; +Cc: palmer@dabbelt.com
On Tue, 2020-07-07 at 18:09 +0800, lazyparser@gmail.com wrote:
> From: Wei Wu <lazyparser@gmail.com>
>
> `imm20` operand type is used in LUI/AUIPC and other instructions.
> The value should not be left shifted 12bits for disassembly output.
>
> Signed-off-by: Wei Wu <lazyparser@gmail.com>
Hello,
Thanks for the patch.
Can you please send it again and make sure you CC the QEMU mailing
list? https://lists.nongnu.org/mailman/listinfo/qemu-devel
Alistair
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 278d9be924..a2b6472bd8 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
>
> static int32_t operand_imm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 44) << 12;
> + return ((int64_t)inst << 32) >> 44;
> }
>
> static int32_t operand_jimm20(rv_inst inst)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
@ 2020-07-07 15:43 Wei Wu
2020-07-10 18:30 ` Richard Henderson
0 siblings, 1 reply; 6+ messages in thread
From: Wei Wu @ 2020-07-07 15:43 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair.Francis, palmer, Wei Wu
`imm20` operand type is used in LUI/AUIPC and other instructions.
The value should not be left shifted 12bits for disassembly output.
Signed-off-by: Wei Wu <lazyparser@gmail.com>
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 278d9be924..a2b6472bd8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
static int32_t operand_imm20(rv_inst inst)
{
- return (((int64_t)inst << 32) >> 44) << 12;
+ return ((int64_t)inst << 32) >> 44;
}
static int32_t operand_jimm20(rv_inst inst)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
2020-07-07 15:15 ` Alistair Francis
@ 2020-07-07 15:47 ` Wei Wu (吴伟)
0 siblings, 0 replies; 6+ messages in thread
From: Wei Wu (吴伟) @ 2020-07-07 15:47 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com
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Hi Alistair,
Thank you for your quick response. I've sent the patch to the qemu-devel.
On Tue, Jul 7, 2020 at 11:15 PM Alistair Francis <Alistair.Francis@wdc.com>
wrote:
> On Tue, 2020-07-07 at 18:09 +0800, lazyparser@gmail.com wrote:
> > From: Wei Wu <lazyparser@gmail.com>
> >
> > `imm20` operand type is used in LUI/AUIPC and other instructions.
> > The value should not be left shifted 12bits for disassembly output.
> >
> > Signed-off-by: Wei Wu <lazyparser@gmail.com>
>
> Hello,
>
> Thanks for the patch.
>
> Can you please send it again and make sure you CC the QEMU mailing
> list? https://lists.nongnu.org/mailman/listinfo/qemu-devel
>
> Alistair
>
> > ---
> > disas/riscv.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/disas/riscv.c b/disas/riscv.c
> > index 278d9be924..a2b6472bd8 100644
> > --- a/disas/riscv.c
> > +++ b/disas/riscv.c
> > @@ -2083,7 +2083,7 @@ static int32_t operand_imm12(rv_inst inst)
> >
> > static int32_t operand_imm20(rv_inst inst)
> > {
> > - return (((int64_t)inst << 32) >> 44) << 12;
> > + return ((int64_t)inst << 32) >> 44;
> > }
> >
> > static int32_t operand_jimm20(rv_inst inst)
>
--
Best wishes,
Wei Wu (吴伟)
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand.
2020-07-07 15:43 Wei Wu
@ 2020-07-10 18:30 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-07-10 18:30 UTC (permalink / raw)
To: Wei Wu, qemu-devel; +Cc: palmer, Alistair.Francis
On 7/7/20 8:43 AM, Wei Wu wrote:
> static int32_t operand_imm20(rv_inst inst)
> {
> - return (((int64_t)inst << 32) >> 44) << 12;
> + return ((int64_t)inst << 32) >> 44;
> }
There's no point in casting to int64_t, for one. But it would be better to use
sextract32(inst, 12, 20).
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-07-10 18:32 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2020-07-07 10:09 [PATCH] disas/riscv: Fix incorrect disassembly for `imm20` operand lazyparser
2020-07-07 15:15 ` Alistair Francis
2020-07-07 15:47 ` Wei Wu (吴伟)
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2020-07-07 15:43 Wei Wu
2020-07-10 18:30 ` Richard Henderson
2020-07-07 8:20 Wei Wu (吴伟)
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