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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: Lyude Paul <lyude@redhat.com>, Bjorn Helgaas <helgaas@kernel.org>,
	Karol Herbst <kherbst@redhat.com>,
	Sasha Levin <sashal@kernel.org>,
	Patrick Volkerding <volkerdi@gmail.com>,
	Linux PCI <linux-pci@vger.kernel.org>,
	linux-kernel@vger.kernel.org,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Kai-Heng Feng <kai.heng.feng@canonical.com>,
	Ben Skeggs <bskeggs@redhat.com>,
	nouveau <nouveau@lists.freedesktop.org>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: nouveau regression with 5.7 caused by "PCI/PM: Assume ports without DLL Link Active train links in 100 ms"
Date: Tue, 21 Jul 2020 16:08:47 +0300	[thread overview]
Message-ID: <20200721130847.GK5180@lahna.fi.intel.com> (raw)
In-Reply-To: <20200717195209.vmtyfmgweoo645lh@wunner.de>

On Fri, Jul 17, 2020 at 09:52:09PM +0200, Lukas Wunner wrote:
> On Fri, Jul 17, 2020 at 03:04:10PM -0400, Lyude Paul wrote:
> > Isn't it possible to tell whether a PCI device is connected through
> > thunderbolt or not? We could probably get away with just defaulting
> > to 100ms for thunderbolt devices without DLL Link Active specified,
> > and then default to the old delay value for non-thunderbolt devices.
> 
> pci_is_thunderbolt_attached()

That only works with some devices. I think we should try to keep the
fact that some PCIe links may be tunneled over TBT/USB4 transparent to
the PCI core and try to treat them as "standard" PCIe links if possible
at all :)

WARNING: multiple messages have this Message-ID (diff)
From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Lukas Wunner <lukas@wunner.de>
Cc: Sasha Levin <sashal@kernel.org>,
	Karol Herbst <kherbst@redhat.com>,
	Patrick Volkerding <volkerdi@gmail.com>,
	Linux PCI <linux-pci@vger.kernel.org>,
	linux-kernel@vger.kernel.org,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Kai-Heng Feng <kai.heng.feng@canonical.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	Ben Skeggs <bskeggs@redhat.com>,
	nouveau <nouveau@lists.freedesktop.org>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: nouveau regression with 5.7 caused by "PCI/PM: Assume ports without DLL Link Active train links in 100 ms"
Date: Tue, 21 Jul 2020 16:08:47 +0300	[thread overview]
Message-ID: <20200721130847.GK5180@lahna.fi.intel.com> (raw)
In-Reply-To: <20200717195209.vmtyfmgweoo645lh@wunner.de>

On Fri, Jul 17, 2020 at 09:52:09PM +0200, Lukas Wunner wrote:
> On Fri, Jul 17, 2020 at 03:04:10PM -0400, Lyude Paul wrote:
> > Isn't it possible to tell whether a PCI device is connected through
> > thunderbolt or not? We could probably get away with just defaulting
> > to 100ms for thunderbolt devices without DLL Link Active specified,
> > and then default to the old delay value for non-thunderbolt devices.
> 
> pci_is_thunderbolt_attached()

That only works with some devices. I think we should try to keep the
fact that some PCIe links may be tunneled over TBT/USB4 transparent to
the PCI core and try to treat them as "standard" PCIe links if possible
at all :)
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

  reply	other threads:[~2020-07-21 13:08 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07 19:30 nouveau regression with 5.7 caused by "PCI/PM: Assume ports without DLL Link Active train links in 100 ms" Karol Herbst
2020-07-16 22:10 ` Karol Herbst
2020-07-16 22:10   ` Karol Herbst
2020-07-16 23:54   ` Bjorn Helgaas
2020-07-16 23:54     ` Bjorn Helgaas
2020-07-17  0:43     ` Karol Herbst
2020-07-17  0:43       ` Karol Herbst
2020-07-17  0:43       ` Karol Herbst
2020-07-17 11:32       ` Karol Herbst
2020-07-17 11:32         ` Karol Herbst
2020-07-21 12:22         ` Mika Westerberg
2020-07-21 12:22           ` Mika Westerberg
2020-07-21 15:01           ` Lyude Paul
2020-07-21 15:01             ` Lyude Paul
2020-07-21 15:27             ` Mika Westerberg
2020-07-21 15:27               ` Mika Westerberg
2020-07-21 16:00               ` Lyude Paul
2020-07-21 16:00                 ` Lyude Paul
2020-07-21 18:24                 ` Lyude Paul
2020-07-21 18:24                   ` Lyude Paul
2020-07-21 18:24                   ` Lyude Paul
2020-07-22  9:23                   ` Mika Westerberg
2020-07-22  9:23                     ` Mika Westerberg
2020-07-21 18:37               ` Patrick Volkerding
2020-07-21 18:37                 ` Patrick Volkerding
2020-07-22  9:25                 ` Mika Westerberg
2020-07-22  9:25                   ` Mika Westerberg
2020-07-22  9:25                   ` Mika Westerberg
2020-07-23 20:30                   ` Karol Herbst
2020-07-23 20:30                     ` Karol Herbst
2020-07-24  9:57                     ` Mika Westerberg
2020-07-24  9:57                       ` Mika Westerberg
2020-07-24 14:35                       ` Bjorn Helgaas
2020-07-24 14:35                         ` Bjorn Helgaas
2020-07-17 14:43       ` Sasha Levin
2020-07-17 14:43         ` Sasha Levin
2020-07-17 22:59         ` Bjorn Helgaas
2020-07-17 22:59           ` Bjorn Helgaas
2020-07-17 19:04     ` Lyude Paul
2020-07-17 19:04       ` Lyude Paul
2020-07-17 19:04       ` Lyude Paul
2020-07-17 19:52       ` Lukas Wunner
2020-07-17 19:52         ` Lukas Wunner
2020-07-21 13:08         ` Mika Westerberg [this message]
2020-07-21 13:08           ` Mika Westerberg

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