From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Linux-ALSA <alsa-devel@alsa-project.org>,
Timur Tabi <timur@kernel.org>, Xiubo Li <Xiubo.Lee@gmail.com>,
Fabio Estevam <festevam@gmail.com>,
Shengjiu Wang <shengjiu.wang@nxp.com>,
Takashi Iwai <tiwai@suse.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
linuxppc-dev@lists.ozlabs.org,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ASoC: fsl_sai: Clean code for synchronize mode
Date: Mon, 3 Aug 2020 20:00:05 -0700 [thread overview]
Message-ID: <20200804030004.GA27028@Asurada-Nvidia> (raw)
In-Reply-To: <CAA+D8ANagfMXPAkK4-vBDY9rZMukVUXs8FfBCHS0avXt57pekA@mail.gmail.com>
On Tue, Aug 04, 2020 at 10:35:12AM +0800, Shengjiu Wang wrote:
> On Tue, Aug 4, 2020 at 10:11 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> >
> > On Tue, Aug 04, 2020 at 09:39:44AM +0800, Shengjiu Wang wrote:
> > > On Tue, Aug 4, 2020 at 5:57 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> > > >
> > > > On Mon, Aug 03, 2020 at 04:04:23PM +0800, Shengjiu Wang wrote:
> > > >
> > > > > > > clock generation. The TCSR.TE is no need to enabled when only RX
> > > > > > > is enabled.
> > > > > >
> > > > > > You are correct if there's only RX running without TX joining.
> > > > > > However, that's something we can't guarantee. Then we'd enable
> > > > > > TE after RE is enabled, which is against what RM recommends:
> > > > > >
> > > > > > # From 54.3.3.1 Synchronous mode in IMX6SXRM
> > > > > > # If the receiver bit clock and frame sync are to be used by
> > > > > > # both the transmitter and receiver, it is recommended that
> > > > > > # the receiver is the last enabled and the first disabled.
> > > > > >
> > > > > > I remember I did this "ugly" design by strictly following what
> > > > > > RM says. If hardware team has updated the RM or removed this
> > > > > > limitation, please quote in the commit logs.
> > > > >
> > > > > There is no change in RM and same recommandation.
> > > > >
> > > > > My change does not violate the RM. The direction which generates
> > > > > the clock is still last enabled.
> > > >
> > > > Using Tx syncing with Rx clock for example,
> > > > T1: arecord (non-stop) => set RE
> > > > T2: aplay => set TE then RE (but RE is already set at T1)
> > > >
> > > > Anything that I am missing?
> > >
> > > This is a good example.
> > > We have used this change locally for a long time, so I think it is
> > > safe to do this change, a little different with the recommandation.
> >
> > Any reason for we have to go against the recommendation?
>
> Previous code will enable TE and RE together even for asynchronous
> mode.
> And for recommendation, previous code just consider the RX sync with
> TX, but still violates the recommendation for TX sync with RX case.
> So at least this new change is some kind of improvement.
Okay. Let's change it then. Please make sure to update/remove
those old comments in the trigger(). And it's probably better
to mention that what we do now is a bit different from RM:
/*
* Enable the opposite direction for synchronous mode
* 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
* 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
*
* RM recommends to enable RE after TE for case 1 and to enable
* TE after RE for case 2, but we here may not always guarantee
* that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
* TE after RE, which is against what RM recommends but should
* be safe to do, judging by years of testing results.
*/
Btw, do we need similar change for TRIGGER_STOP?
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Shengjiu Wang <shengjiu.wang@nxp.com>,
Linux-ALSA <alsa-devel@alsa-project.org>,
Timur Tabi <timur@kernel.org>, Xiubo Li <Xiubo.Lee@gmail.com>,
linuxppc-dev@lists.ozlabs.org, Takashi Iwai <tiwai@suse.com>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] ASoC: fsl_sai: Clean code for synchronize mode
Date: Mon, 3 Aug 2020 20:00:05 -0700 [thread overview]
Message-ID: <20200804030004.GA27028@Asurada-Nvidia> (raw)
In-Reply-To: <CAA+D8ANagfMXPAkK4-vBDY9rZMukVUXs8FfBCHS0avXt57pekA@mail.gmail.com>
On Tue, Aug 04, 2020 at 10:35:12AM +0800, Shengjiu Wang wrote:
> On Tue, Aug 4, 2020 at 10:11 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> >
> > On Tue, Aug 04, 2020 at 09:39:44AM +0800, Shengjiu Wang wrote:
> > > On Tue, Aug 4, 2020 at 5:57 AM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> > > >
> > > > On Mon, Aug 03, 2020 at 04:04:23PM +0800, Shengjiu Wang wrote:
> > > >
> > > > > > > clock generation. The TCSR.TE is no need to enabled when only RX
> > > > > > > is enabled.
> > > > > >
> > > > > > You are correct if there's only RX running without TX joining.
> > > > > > However, that's something we can't guarantee. Then we'd enable
> > > > > > TE after RE is enabled, which is against what RM recommends:
> > > > > >
> > > > > > # From 54.3.3.1 Synchronous mode in IMX6SXRM
> > > > > > # If the receiver bit clock and frame sync are to be used by
> > > > > > # both the transmitter and receiver, it is recommended that
> > > > > > # the receiver is the last enabled and the first disabled.
> > > > > >
> > > > > > I remember I did this "ugly" design by strictly following what
> > > > > > RM says. If hardware team has updated the RM or removed this
> > > > > > limitation, please quote in the commit logs.
> > > > >
> > > > > There is no change in RM and same recommandation.
> > > > >
> > > > > My change does not violate the RM. The direction which generates
> > > > > the clock is still last enabled.
> > > >
> > > > Using Tx syncing with Rx clock for example,
> > > > T1: arecord (non-stop) => set RE
> > > > T2: aplay => set TE then RE (but RE is already set at T1)
> > > >
> > > > Anything that I am missing?
> > >
> > > This is a good example.
> > > We have used this change locally for a long time, so I think it is
> > > safe to do this change, a little different with the recommandation.
> >
> > Any reason for we have to go against the recommendation?
>
> Previous code will enable TE and RE together even for asynchronous
> mode.
> And for recommendation, previous code just consider the RX sync with
> TX, but still violates the recommendation for TX sync with RX case.
> So at least this new change is some kind of improvement.
Okay. Let's change it then. Please make sure to update/remove
those old comments in the trigger(). And it's probably better
to mention that what we do now is a bit different from RM:
/*
* Enable the opposite direction for synchronous mode
* 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx
* 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx
*
* RM recommends to enable RE after TE for case 1 and to enable
* TE after RE for case 2, but we here may not always guarantee
* that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables
* TE after RE, which is against what RM recommends but should
* be safe to do, judging by years of testing results.
*/
Btw, do we need similar change for TRIGGER_STOP?
next prev parent reply other threads:[~2020-08-04 3:01 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 3:17 [PATCH] ASoC: fsl_sai: Clean code for synchronize mode Shengjiu Wang
2020-08-03 5:40 ` Nicolin Chen
2020-08-03 5:40 ` Nicolin Chen
2020-08-03 5:40 ` Nicolin Chen
2020-08-03 8:04 ` Shengjiu Wang
2020-08-03 8:04 ` Shengjiu Wang
2020-08-03 21:57 ` Nicolin Chen
2020-08-03 21:57 ` Nicolin Chen
2020-08-04 1:39 ` Shengjiu Wang
2020-08-04 1:39 ` Shengjiu Wang
2020-08-04 2:11 ` Nicolin Chen
2020-08-04 2:11 ` Nicolin Chen
2020-08-04 2:35 ` Shengjiu Wang
2020-08-04 2:35 ` Shengjiu Wang
2020-08-04 3:00 ` Nicolin Chen [this message]
2020-08-04 3:00 ` Nicolin Chen
2020-08-04 3:23 ` Shengjiu Wang
2020-08-04 3:23 ` Shengjiu Wang
2020-08-04 4:22 ` Shengjiu Wang
2020-08-04 4:22 ` Shengjiu Wang
2020-08-04 7:03 ` Nicolin Chen
2020-08-04 7:03 ` Nicolin Chen
2020-08-04 7:08 ` Nicolin Chen
2020-08-04 7:08 ` Nicolin Chen
2020-08-04 7:53 ` Shengjiu Wang
2020-08-04 7:53 ` Shengjiu Wang
2020-08-04 8:13 ` Nicolin Chen
2020-08-04 8:13 ` Nicolin Chen
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