[PATCH 0/5] add SATA/AHCI support for BananaPi R64

[PATCH 0/5] add SATA/AHCI support for BananaPi R64

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

BananaPi R64 has an SATA socket where an HDD can be connected.
I have ported Linux Driver to Uboot and can access my harddrive

BPI-R64> scsi scan
scanning bus for devices...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: ncq stag pm clo only pmp pio slum part ccc apst 
  Device 0: (0:0) Vendor: ATA Prod.: ST750LM022 HN-M7 Rev: 2AR1
            Type: Hard Disk
            Capacity: 715404.8 MB = 698.6 GB (1465149168 x 512)
BPI-R64> ls scsi 0:1
            EFI/
      512   BOOTSECT.BAK

1 file(s), 1 dir(s)

BPI-R64>

this Series is based on 2020.10-rc1 + mt7622 PCIe series [1]

[1] https://patchwork.ozlabs.org/project/uboot/list/?series=194888

Frank Wunderlich (5):
  arm: dts: mt7622: add SATA reset constants
  phy: mtk-tphy: add PHY_TYPE_SATA
  reset: add basic reset controller for pciesys
  ahci: mediatek: add ahci driver
  dts: r64: add sata- and asm_sel nodes

 arch/arm/dts/mt7622-bpi-r64.dts          |   9 ++
 arch/arm/dts/mt7622.dtsi                 |  44 +++++
 drivers/ata/Kconfig                      |   8 +
 drivers/ata/Makefile                     |   1 +
 drivers/ata/mtk_ahci.c                   | 194 +++++++++++++++++++++++
 drivers/clk/mediatek/clk-mt7622.c        |  15 ++
 drivers/phy/phy-mtk-tphy.c               | 105 ++++++++++++
 include/dt-bindings/reset/mt7629-reset.h |   5 +-
 8 files changed, 380 insertions(+), 1 deletion(-)
 create mode 100644 drivers/ata/mtk_ahci.c

-- 
2.25.1

[PATCH 1/5] arm: dts: mt7622: add SATA reset constants

[Frank Wunderlich]

add reset constants used for SATA to header file

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 include/dt-bindings/reset/mt7629-reset.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h
index 8f1634f7a6..311a5cb3d0 100644
--- a/include/dt-bindings/reset/mt7629-reset.h
+++ b/include/dt-bindings/reset/mt7629-reset.h
@@ -6,7 +6,10 @@
 #ifndef _DT_BINDINGS_MTK_RESET_H_
 #define _DT_BINDINGS_MTK_RESET_H_
 
-/* PCIe Subsystem resets */
+/* PCIe/SATA Subsystem resets */
+#define MT7622_SATA_PHY_REG_RST			12
+#define MT7622_SATA_PHY_SW_RST			13
+#define MT7622_SATA_AXI_BUS_RST			15
 #define PCIE1_CORE_RST			19
 #define PCIE1_MMIO_RST			20
 #define PCIE1_HRST			21
-- 
2.25.1

[PATCH 2/5] phy: mtk-tphy: add PHY_TYPE_SATA

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

add support for PHY_TYPE_SATA to Mediateks TPHY driver

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 drivers/phy/phy-mtk-tphy.c | 105 +++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 1e65c24356..326227a30d 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -175,6 +175,65 @@
 #define XC3_RG_U3_XTAL_RX_PWD		BIT(9)
 #define XC3_RG_U3_FRC_XTAL_RX_PWD	BIT(8)
 
+/* SATA register setting */
+#define PHYD_CTRL_SIGNAL_MODE4		0x1c
+/* CDR Charge Pump P-path current adjustment */
+#define RG_CDR_BICLTD1_GEN1_MSK		GENMASK(23, 20)
+#define RG_CDR_BICLTD1_GEN1_VAL(x)	((0xf & (x)) << 20)
+#define RG_CDR_BICLTD0_GEN1_MSK		GENMASK(11, 8)
+#define RG_CDR_BICLTD0_GEN1_VAL(x)	((0xf & (x)) << 8)
+
+#define PHYD_DESIGN_OPTION2		0x24
+/* Symbol lock count selection */
+#define RG_LOCK_CNT_SEL_MSK		GENMASK(5, 4)
+#define RG_LOCK_CNT_SEL_VAL(x)		((0x3 & (x)) << 4)
+
+#define PHYD_DESIGN_OPTION9		0x40
+/* COMWAK GAP width window */
+#define RG_TG_MAX_MSK			GENMASK(20, 16)
+#define RG_TG_MAX_VAL(x)		((0x1f & (x)) << 16)
+/* COMINIT GAP width window */
+#define RG_T2_MAX_MSK			GENMASK(13, 8)
+#define RG_T2_MAX_VAL(x)		((0x3f & (x)) << 8)
+/* COMWAK GAP width window */
+#define RG_TG_MIN_MSK			GENMASK(7, 5)
+#define RG_TG_MIN_VAL(x)		((0x7 & (x)) << 5)
+/* COMINIT GAP width window */
+#define RG_T2_MIN_MSK			GENMASK(4, 0)
+#define RG_T2_MIN_VAL(x)		(0x1f & (x))
+
+#define ANA_RG_CTRL_SIGNAL1		0x4c
+/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
+#define RG_IDRV_0DB_GEN1_MSK		GENMASK(13, 8)
+#define RG_IDRV_0DB_GEN1_VAL(x)		((0x3f & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL4		0x58
+#define RG_CDR_BICLTR_GEN1_MSK		GENMASK(23, 20)
+#define RG_CDR_BICLTR_GEN1_VAL(x)	((0xf & (x)) << 20)
+/* Loop filter R1 resistance adjustment for Gen1 speed */
+#define RG_CDR_BR_GEN2_MSK		GENMASK(10, 8)
+#define RG_CDR_BR_GEN2_VAL(x)		((0x7 & (x)) << 8)
+
+#define ANA_RG_CTRL_SIGNAL6		0x60
+/* I-path capacitance adjustment for Gen1 */
+#define RG_CDR_BC_GEN1_MSK		GENMASK(28, 24)
+#define RG_CDR_BC_GEN1_VAL(x)		((0x1f & (x)) << 24)
+#define RG_CDR_BIRLTR_GEN1_MSK		GENMASK(4, 0)
+#define RG_CDR_BIRLTR_GEN1_VAL(x)	(0x1f & (x))
+
+#define ANA_EQ_EYE_CTRL_SIGNAL1		0x6c
+/* RX Gen1 LEQ tuning step */
+#define RG_EQ_DLEQ_LFI_GEN1_MSK		GENMASK(11, 8)
+#define RG_EQ_DLEQ_LFI_GEN1_VAL(x)	((0xf & (x)) << 8)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL4		0xd8
+#define RG_CDR_BIRLTD0_GEN1_MSK		GENMASK(20, 16)
+#define RG_CDR_BIRLTD0_GEN1_VAL(x)	((0x1f & (x)) << 16)
+
+#define ANA_EQ_EYE_CTRL_SIGNAL5		0xdc
+#define RG_CDR_BIRLTD0_GEN3_MSK		GENMASK(4, 0)
+#define RG_CDR_BIRLTD0_GEN3_VAL(x)	(0x1f & (x))
+
 enum mtk_phy_version {
 	MTK_TPHY_V1 = 1,
 	MTK_TPHY_V2,
@@ -372,6 +431,45 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 	udelay(3000);
 }
 
+static void sata_phy_instance_init(struct mtk_tphy *tphy,
+				   struct mtk_phy_instance *instance)
+{
+	struct u3phy_banks *u3_banks = &instance->u3_banks;
+
+	clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
+			RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
+			RG_CDR_BIRLTR_GEN1_VAL(0x6) |
+			RG_CDR_BC_GEN1_VAL(0x1a));
+	clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
+			RG_CDR_BIRLTD0_GEN1_MSK,
+			RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+	clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
+			RG_CDR_BIRLTD0_GEN3_MSK,
+			RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+	clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
+			RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
+			RG_CDR_BICLTR_GEN1_VAL(0x0c) |
+			RG_CDR_BR_GEN2_VAL(0x07));
+	clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
+			RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
+			RG_CDR_BICLTD0_GEN1_VAL(0x08) |
+			RG_CDR_BICLTD1_GEN1_VAL(0x02));
+	clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
+			RG_LOCK_CNT_SEL_MSK,
+			RG_LOCK_CNT_SEL_VAL(0x02));
+	clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
+			RG_T2_MIN_MSK | RG_TG_MIN_MSK |
+			RG_T2_MAX_MSK | RG_TG_MAX_MSK,
+			RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
+			RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
+	clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1,
+			RG_IDRV_0DB_GEN1_MSK,
+			RG_IDRV_0DB_GEN1_VAL(0x20));
+	clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1,
+			RG_EQ_DLEQ_LFI_GEN1_MSK,
+			RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
+}
+
 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 				       struct mtk_phy_instance *instance)
 {
@@ -414,6 +512,9 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy,
 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 		break;
+	case PHY_TYPE_SATA:
+		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
+		break;
 	default:
 		dev_err(tphy->dev, "incompatible PHY type\n");
 		return;
@@ -474,6 +575,9 @@ static int mtk_phy_init(struct phy *phy)
 	case PHY_TYPE_PCIE:
 		pcie_phy_instance_init(tphy, instance);
 		break;
+	case PHY_TYPE_SATA:
+		sata_phy_instance_init(tphy, instance);
+		break;
 	default:
 		dev_err(tphy->dev, "incompatible PHY type\n");
 		return -EINVAL;
@@ -552,6 +656,7 @@ static int mtk_phy_xlate(struct phy *phy,
 	instance->type = args->args[1];
 	if (!(instance->type == PHY_TYPE_USB2 ||
 	      instance->type == PHY_TYPE_USB3 ||
+	      instance->type == PHY_TYPE_SATA ||
 	      instance->type == PHY_TYPE_PCIE)) {
 		dev_err(phy->dev, "unsupported device type\n");
 		return -EINVAL;
-- 
2.25.1

[PATCH 3/5] reset: add basic reset controller for pciesys

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

bind reset controller to pciesys

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index bd86b5b974..95c5232957 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev)
 	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
 }
 
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+//	PCIESYS uses in linux also 0x34 = ETHSYS reset controller
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+#endif
+
+	return ret;
+}
+
 static int mt7622_ethsys_probe(struct udevice *dev)
 {
 	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7622_pciesys_compat,
 	.probe = mt7622_pciesys_probe,
+	.bind = mt7622_pciesys_bind,
 	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 };
-- 
2.25.1

[PATCH 4/5] ahci: mediatek: add ahci driver

[Frank Wunderlich]

add AHCI driver ported from linux

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 drivers/ata/Kconfig    |   8 ++
 drivers/ata/Makefile   |   1 +
 drivers/ata/mtk_ahci.c | 194 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+)
 create mode 100644 drivers/ata/mtk_ahci.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index d8c9756c2a..f2f8275aec 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -130,4 +130,12 @@ config AHCI_MVEBU
 	  onboard AHCI SATA.
 
 	  If unsure, say N.
+
+config MTK_AHCI
+	bool "Enable Mediatek AHCI driver support"
+	depends on AHCI
+	help
+	  Enable this driver to support Sata devices through
+	  Mediatek AHCI controller (e.g. MT7622).
+
 endmenu
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a69edb10f7..98fb480700 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_SANDBOX) += sata_sandbox.o
 obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
 obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o
+obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o
diff --git a/drivers/ata/mtk_ahci.c b/drivers/ata/mtk_ahci.c
new file mode 100644
index 0000000000..25a3c97906
--- /dev/null
+++ b/drivers/ata/mtk_ahci.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * MTK SATA platform driver
+ *
+ * (C) Copyright 2020
+ *     Mediatek
+ *
+ * Author: Frank Wunderlich <frank-w@public-files.de>
+ * based on https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/ata/ahci_mtk.c
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <sata.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <generic-phy.h>
+#include <dm/of_access.h>
+#include <syscon.h>
+#include <linux/err.h>
+#include <regmap.h>
+
+#define SYS_CFG			0x14
+#define SYS_CFG_SATA_MSK	GENMASK(31, 30)
+#define SYS_CFG_SATA_EN		BIT(31)
+
+struct mtk_ahci_priv {
+	void *base;
+
+	struct regmap *mode;
+	struct reset_ctl axi_rst;
+	struct reset_ctl sw_rst;
+	struct reset_ctl reg_rst;
+};
+
+static int mtk_ahci_bind(struct udevice *dev)
+{
+	struct udevice *scsi_dev;
+
+	return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int mtk_ahci_ofdata_to_platdata(struct udevice *dev)
+{
+	struct mtk_ahci_priv *priv = dev_get_priv(dev);
+
+	priv->base = map_physmem(devfdt_get_addr(dev), sizeof(void *),
+				 MAP_NOCACHE);
+
+	return 0;
+}
+
+static int mtk_ahci_platform_resets(struct udevice *dev)
+{
+	struct mtk_ahci_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret=reset_get_by_name(dev, "axi",&priv->axi_rst);
+	if (ret) {
+		pr_err("unable to find reset controller 'axi'\n");
+		return ret;
+	}
+
+	ret=reset_get_by_name(dev, "sw",&priv->sw_rst);
+	if (ret) {
+		pr_err("unable to find reset controller 'sw'\n");
+		return ret;
+	}
+
+	ret=reset_get_by_name(dev, "reg",&priv->reg_rst);
+	if (ret) {
+		pr_err("unable to find reset controller 'reg'\n");
+		return ret;
+	}
+
+	ret=reset_assert(&priv->axi_rst);
+	if (ret) {
+		pr_err("unable to assert reset controller 'axi'\n");
+		return ret;
+	}
+
+	ret=reset_assert(&priv->sw_rst);
+	if (ret) {
+		pr_err("unable to assert reset controller 'sw'\n");
+		return ret;
+	}
+
+	ret=reset_assert(&priv->reg_rst);
+	if (ret) {
+		pr_err("unable to assert reset controller 'reg'\n");
+		return ret;
+	}
+
+	ret=reset_deassert(&priv->axi_rst);
+	if (ret) {
+		pr_err("unable to deassert reset controller 'axi'\n");
+		return ret;
+	}
+
+	ret=reset_deassert(&priv->sw_rst);
+	if (ret) {
+		pr_err("unable to deassert reset controller 'sw'\n");
+		return ret;
+	}
+
+	ret=reset_deassert(&priv->reg_rst);
+	if (ret) {
+		pr_err("unable to deassert reset controller 'reg'\n");
+		return ret;
+	}
+	return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_uc_priv *hpriv,struct udevice *dev)
+{
+	struct mtk_ahci_priv *plat = dev_get_priv(dev);
+	const void *fdt = gd->fdt_blob;
+
+	/* enable SATA function if needed */
+	if (fdt_get_property(fdt, dev_of_offset(dev),"mediatek,phy-mode", NULL)) {
+		plat->mode = syscon_regmap_lookup_by_phandle(
+					dev, "mediatek,phy-mode");
+		if (IS_ERR(plat->mode)) {
+			dev_err(dev, "missing phy-mode phandle\n");
+			return PTR_ERR(plat->mode);
+		}
+		regmap_update_bits(plat->mode, SYS_CFG, SYS_CFG_SATA_MSK,
+				   SYS_CFG_SATA_EN);
+	}
+
+	ofnode_read_u32(dev->node, "ports-implemented", &hpriv->port_map);
+	return 0;
+}
+
+static int mtk_ahci_probe(struct udevice *dev)
+{
+	struct mtk_ahci_priv *priv = dev_get_priv(dev);
+	int ret;
+	struct phy phy;
+	struct ahci_uc_priv *hpriv;
+
+	hpriv = malloc(sizeof(struct ahci_uc_priv));
+	if (!hpriv)
+		return -ENOMEM;
+
+	memset(hpriv, 0, sizeof(struct ahci_uc_priv));
+
+	ret = mtk_ahci_parse_property(hpriv,dev);
+	if (ret)
+		return ret;
+
+	ret = mtk_ahci_platform_resets(dev);
+	if (ret)
+		return ret;
+
+	ret = generic_phy_get_by_name(dev, "sata-phy", &phy);
+	if (ret) {
+		pr_err("can't get the phy from DT\n");
+		return ret;
+	}
+
+	ret = generic_phy_init(&phy);
+	if (ret) {
+		pr_err("unable to initialize the sata phy\n");
+		return ret;
+	}
+
+	ret = generic_phy_power_on(&phy);
+	if (ret) {
+		pr_err("unable to power on the sata phy\n");
+		return ret;
+	}
+
+	return ahci_probe_scsi(dev, (ulong)priv->base);
+}
+
+static const struct udevice_id mtk_ahci_ids[] = {
+	{ .compatible = "mediatek,mtk-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(mtk_ahci) = {
+	.name	= "mtk_ahci",
+	.id	= UCLASS_AHCI,
+	.of_match = mtk_ahci_ids,
+	.bind	= mtk_ahci_bind,
+	.ofdata_to_platdata = mtk_ahci_ofdata_to_platdata,
+	.ops	= &scsi_ops,
+	.probe	= mtk_ahci_probe,
+	.priv_auto_alloc_size = sizeof(struct mtk_ahci_priv),
+};
-- 
2.25.1

[PATCH 5/5] dts: r64: add sata- and asm_sel nodes

[Frank Wunderlich]

From: Frank Wunderlich <frank-w@public-files.de>

asm_sel is for switching between sata and pcie mode
on r64 there is GPIO90 connected to ASM1480 which
switches RX/TX pairs to PCIe/SATA connector
output-low means sata-controller is active

with 2020-10 now reg is also needed for the phy itself

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 arch/arm/dts/mt7622-bpi-r64.dts |  9 +++++++
 arch/arm/dts/mt7622.dtsi        | 44 +++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)

diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts
index c89e816878..51287cea3a 100644
--- a/arch/arm/dts/mt7622-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bpi-r64.dts
@@ -235,3 +235,12 @@
 		full-duplex;
 	};
 };
+
+&gpio {
+	/*gpio 90 for setting mode to sata*/
+	asm_sel {
+		gpio-hog;
+		gpios = <90 GPIO_ACTIVE_HIGH>;
+		output-low;
+	};
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index fec071643e..2802909671 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/power/mt7629-power.h>
 #include <dt-bindings/reset/mt7629-reset.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	compatible = "mediatek,mt7622";
@@ -270,6 +271,49 @@
 		};
 	};
 
+	sata: sata at 1a200000 {
+		compatible = "mediatek,mtk-ahci";
+//		reg = <0 0x1a200000 0 0x1100>;
+		reg = <0x1a200000 0x1100>;
+		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+			<&pciesys MT7622_SATA_PHY_SW_RST>,
+			<&pciesys MT7622_SATA_PHY_REG_RST>;
+		reset-names = "axi", "sw", "reg";
+		mediatek,phy-mode = <&pciesys>;
+		ports-implemented = <0x1>;
+/*
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hostc";
+		clocks = <&pciesys CLK_SATA_AHB_EN>,
+			<&pciesys CLK_SATA_AXI_EN>,
+			<&pciesys CLK_SATA_ASIC_EN>,
+			<&pciesys CLK_SATA_RBC_EN>,
+			<&pciesys CLK_SATA_PM_EN>;
+			clock-names = "ahb", "axi", "asic", "rbc", "pm";
+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+		status = "disabled";*/
+		phys = <&sata_port PHY_TYPE_SATA>;
+		phy-names = "sata-phy";
+		status = "okay";
+	};
+
+	sata_phy: sata-phy at 1a243000 {
+		compatible = "mediatek,generic-tphy-v1";
+		reg = <0x1a243000 0x0100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		status = "okay";
+
+		sata_port: sata-phy at 1a243000 {
+			reg = <0x1a243000 0x0100>;
+			clocks = <&topckgen CLK_TOP_ETH_500M>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+			status = "okay";
+		};
+	};
+
 	ethsys: syscon at 1b000000 {
 		compatible = "mediatek,mt7622-ethsys", "syscon";
 		reg = <0x1b000000 0x1000>;
-- 
2.25.1