From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
"Bin Meng" <bin.meng@windriver.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Jason Wang" <jasowang@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org
Subject: Re: [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property
Date: Wed, 2 Sep 2020 12:45:28 +0200 [thread overview]
Message-ID: <20200902104528.GW2954729@toto> (raw)
In-Reply-To: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
On Tue, Sep 01, 2020 at 09:39:06AM +0800, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the PHY address of the PHY connected to GEM is hard-coded
> to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
> all boards. Add a new 'phy-addr' property so that board can specify
> the PHY address for each GEM instance.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Hi Bin,
It looks like there's a change here compared to v2 to keep addr 0
as broadcast?
Perhaps it would be useful to add a comment in the code about it.
Anyway:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - change "phy-addr" default value to BOARD_PHY_ADDRESS
>
> include/hw/net/cadence_gem.h | 2 ++
> hw/net/cadence_gem.c | 5 +++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 54e646f..01c6189 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
> /* Mask of register bits which are write 1 to clear */
> uint32_t regs_w1c[CADENCE_GEM_MAXREG];
>
> + /* PHY address */
> + uint8_t phy_addr;
> /* PHY registers backing store */
> uint16_t phy_regs[32];
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index a93b5c0..d80096b 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
> uint32_t phy_addr, reg_num;
>
> phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
> - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> + if (phy_addr == s->phy_addr || phy_addr == 0) {
> reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
> retval &= 0xFFFF0000;
> retval |= gem_phy_read(s, reg_num);
> @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
> uint32_t phy_addr, reg_num;
>
> phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
> - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> + if (phy_addr == s->phy_addr || phy_addr == 0) {
> reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
> gem_phy_write(s, reg_num, val);
> }
> @@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
> DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
> DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
> GEM_MODID_VALUE),
> + DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
> DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
> num_priority_queues, 1),
> DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
> --
> 2.7.4
>
WARNING: multiple messages have this Message-ID (diff)
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
qemu-riscv@nongnu.org, "Jason Wang" <jasowang@redhat.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Alistair Francis" <alistair@alistair23.me>
Subject: Re: [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property
Date: Wed, 2 Sep 2020 12:45:28 +0200 [thread overview]
Message-ID: <20200902104528.GW2954729@toto> (raw)
In-Reply-To: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
On Tue, Sep 01, 2020 at 09:39:06AM +0800, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the PHY address of the PHY connected to GEM is hard-coded
> to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
> all boards. Add a new 'phy-addr' property so that board can specify
> the PHY address for each GEM instance.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Hi Bin,
It looks like there's a change here compared to v2 to keep addr 0
as broadcast?
Perhaps it would be useful to add a comment in the code about it.
Anyway:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - change "phy-addr" default value to BOARD_PHY_ADDRESS
>
> include/hw/net/cadence_gem.h | 2 ++
> hw/net/cadence_gem.c | 5 +++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 54e646f..01c6189 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
> /* Mask of register bits which are write 1 to clear */
> uint32_t regs_w1c[CADENCE_GEM_MAXREG];
>
> + /* PHY address */
> + uint8_t phy_addr;
> /* PHY registers backing store */
> uint16_t phy_regs[32];
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index a93b5c0..d80096b 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
> uint32_t phy_addr, reg_num;
>
> phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
> - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> + if (phy_addr == s->phy_addr || phy_addr == 0) {
> reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
> retval &= 0xFFFF0000;
> retval |= gem_phy_read(s, reg_num);
> @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
> uint32_t phy_addr, reg_num;
>
> phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
> - if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
> + if (phy_addr == s->phy_addr || phy_addr == 0) {
> reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
> gem_phy_write(s, reg_num, val);
> }
> @@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
> DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
> DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
> GEM_MODID_VALUE),
> + DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
> DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
> num_priority_queues, 1),
> DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-09-02 10:45 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 1:38 [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 1:38 ` [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 9:36 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 02/16] hw/riscv: hart: " Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-09-01 1:38 ` Bin Meng
2020-09-01 1:39 ` [PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-04 17:47 ` Alistair Francis
2020-09-04 17:47 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 1:39 ` [PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-04 19:30 ` Alistair Francis
2020-09-04 19:30 ` Alistair Francis
2020-09-04 19:30 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:42 ` Philippe Mathieu-Daudé
2020-09-01 10:27 ` Bin Meng
2020-09-01 10:27 ` Bin Meng
2020-09-01 17:56 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` Alistair Francis
2020-09-04 19:08 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-04 20:25 ` Alistair Francis
2020-09-04 20:25 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-04 19:33 ` Alistair Francis
2020-09-04 19:33 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:43 ` Philippe Mathieu-Daudé
2020-09-01 9:43 ` Philippe Mathieu-Daudé
2020-09-02 10:45 ` Edgar E. Iglesias [this message]
2020-09-02 10:45 ` Edgar E. Iglesias
2020-09-04 19:34 ` Alistair Francis
2020-09-04 19:34 ` Alistair Francis
2020-09-04 19:34 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:45 ` Philippe Mathieu-Daudé
2020-09-01 9:45 ` Philippe Mathieu-Daudé
2020-09-02 0:16 ` Alistair Francis
2020-09-02 0:16 ` Alistair Francis
2020-09-02 0:16 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:46 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:47 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-01 9:49 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-09-01 1:39 ` Bin Meng
2020-09-04 19:36 ` Alistair Francis
2020-09-04 19:36 ` Alistair Francis
2020-09-04 20:29 ` [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Alistair Francis
2020-09-04 20:29 ` Alistair Francis
2020-09-06 1:08 ` Leif Lindholm
2020-09-06 1:08 ` Leif Lindholm
2020-09-06 1:08 ` Leif Lindholm
2020-09-07 10:24 ` Bin Meng
2020-09-07 10:24 ` Bin Meng
2020-09-07 10:24 ` Bin Meng
2020-09-07 17:27 ` Leif Lindholm
2020-09-07 17:27 ` Leif Lindholm
2020-09-08 1:15 ` Bin Meng
2020-09-08 1:15 ` Bin Meng
2020-09-08 1:15 ` Bin Meng
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