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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v2 09/14] arm64: dts: imx8mq-phanbell: Align pin configuration group names with schema
Date: Fri,  4 Sep 2020 08:27:38 +0200	[thread overview]
Message-ID: <20200904062743.6273-9-krzk@kernel.org> (raw)
In-Reply-To: <20200904062743.6273-1-krzk@kernel.org>

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 3f541ddf0768..d6d3a3d5abc3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -365,7 +365,7 @@
 		>;
 	};
 
-	pinctrl_pmic: pmicirq {
+	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
 		>;
@@ -395,7 +395,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
@@ -412,7 +412,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
@@ -429,7 +429,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
@@ -448,7 +448,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
@@ -460,7 +460,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-- 
2.17.1


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WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v2 09/14] arm64: dts: imx8mq-phanbell: Align pin configuration group names with schema
Date: Fri,  4 Sep 2020 08:27:38 +0200	[thread overview]
Message-ID: <20200904062743.6273-9-krzk@kernel.org> (raw)
In-Reply-To: <20200904062743.6273-1-krzk@kernel.org>

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 3f541ddf0768..d6d3a3d5abc3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -365,7 +365,7 @@
 		>;
 	};
 
-	pinctrl_pmic: pmicirq {
+	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x41
 		>;
@@ -395,7 +395,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
@@ -412,7 +412,7 @@
 		>;
 	};
 
-	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
 			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
@@ -429,7 +429,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
@@ -448,7 +448,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
@@ -460,7 +460,7 @@
 		>;
 	};
 
-	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
 			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-- 
2.17.1


  parent reply	other threads:[~2020-09-04  6:29 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04  6:27 [PATCH v2 01/14] arm64: dts: imx8mm-beacon: Align pin configuration group names with schema Krzysztof Kozlowski
2020-09-04  6:27 ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 02/14] arm64: dts: imx8mm-evk: Add 32.768 kHz clock to PMIC Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 03/14] arm64: dts: imx8mm-evk: Align pin configuration group names with schema Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 04/14] arm64: dts: imx8mm-ddr4-evk: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 05/14] arm64: dts: imx8mn-ddr4-evk: Align regulator " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 06/14] arm64: dts: imx8mn-evk: Align pin configuration group " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 07/14] arm64: dts: imx8mq-evk: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 08/14] arm64: dts: imx8mq-librem5-devkit: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` Krzysztof Kozlowski [this message]
2020-09-04  6:27   ` [PATCH v2 09/14] arm64: dts: imx8mq-phanbell: " Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 10/14] arm64: dts: imx8mq-pico-pi: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 11/14] arm64: dts: imx8mq-sr-som: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 12/14] arm64: dts: imx8mq-hummingboard-pulse: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 13/14] arm64: dts: imx8qxp-colibri: " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-04  6:27 ` [PATCH v2 14/14] ARM: dts: imx28-m28: Align GPMI NAND node name " Krzysztof Kozlowski
2020-09-04  6:27   ` Krzysztof Kozlowski
2020-09-05  8:05   ` Shawn Guo
2020-09-05  8:05     ` Shawn Guo

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