* [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-22 16:02 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-08-22 16:02 UTC (permalink / raw)
To: iommu; +Cc: intel-gfx, Chris Wilson, James Sewart, Lu Baolu, Joerg Roedel,
stable
Beware that the address size for x86-32 may exceed unsigned long.
[ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
[ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
If we don't handle the wide addresses, the pages are mismapped and the
device read/writes go astray, detected as DMAR faults and leading to
device failure. The behaviour changed (from working to broken) in commit
fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
the error looks older.
Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: James Sewart <jamessewart@arista.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Joerg Roedel <jroedel@suse.de>
Cc: <stable@vger.kernel.org> # v5.3+
---
drivers/iommu/intel/iommu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 2e9c8c3d0da4..ba78a2e854f9 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
return (level - 1) * LEVEL_STRIDE;
}
-static inline int pfn_level_offset(unsigned long pfn, int level)
+static inline int pfn_level_offset(u64 pfn, int level)
{
return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}
-static inline unsigned long level_mask(int level)
+static inline u64 level_mask(int level)
{
- return -1UL << level_to_offset_bits(level);
+ return -1ULL << level_to_offset_bits(level);
}
-static inline unsigned long level_size(int level)
+static inline u64 level_size(int level)
{
- return 1UL << level_to_offset_bits(level);
+ return 1ULL << level_to_offset_bits(level);
}
-static inline unsigned long align_to_level(unsigned long pfn, int level)
+static inline u64 align_to_level(u64 pfn, int level)
{
return (pfn + level_size(level) - 1) & level_mask(level);
}
static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
- return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
+ return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
}
/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-22 16:02 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-08-22 16:02 UTC (permalink / raw)
To: iommu; +Cc: Joerg Roedel, intel-gfx, stable, Chris Wilson
Beware that the address size for x86-32 may exceed unsigned long.
[ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
[ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
If we don't handle the wide addresses, the pages are mismapped and the
device read/writes go astray, detected as DMAR faults and leading to
device failure. The behaviour changed (from working to broken) in commit
fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
the error looks older.
Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: James Sewart <jamessewart@arista.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>
Cc: Joerg Roedel <jroedel@suse.de>
Cc: <stable@vger.kernel.org> # v5.3+
---
drivers/iommu/intel/iommu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 2e9c8c3d0da4..ba78a2e854f9 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
return (level - 1) * LEVEL_STRIDE;
}
-static inline int pfn_level_offset(unsigned long pfn, int level)
+static inline int pfn_level_offset(u64 pfn, int level)
{
return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
}
-static inline unsigned long level_mask(int level)
+static inline u64 level_mask(int level)
{
- return -1UL << level_to_offset_bits(level);
+ return -1ULL << level_to_offset_bits(level);
}
-static inline unsigned long level_size(int level)
+static inline u64 level_size(int level)
{
- return 1UL << level_to_offset_bits(level);
+ return 1ULL << level_to_offset_bits(level);
}
-static inline unsigned long align_to_level(unsigned long pfn, int level)
+static inline u64 align_to_level(u64 pfn, int level)
{
return (pfn + level_size(level) - 1) & level_mask(level);
}
static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
{
- return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
+ return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
}
/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
--
2.20.1
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH] iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
(?)
@ 2020-08-22 16:08 ` Chris Wilson
-1 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-08-22 16:08 UTC (permalink / raw)
To: iommu; +Cc: James Sewart, intel-gfx, Joerg Roedel, stable, Lu Baolu
Quoting Chris Wilson (2020-08-22 17:02:09)
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
Maybe s/u64/dma_addr_t/ ? I'm not sure what is the appropriate type,
just that this makes i915 not try and eat itself. :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-22 16:08 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-08-22 16:08 UTC (permalink / raw)
To: iommu; +Cc: intel-gfx, James Sewart, Lu Baolu, Joerg Roedel, stable
Quoting Chris Wilson (2020-08-22 17:02:09)
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
Maybe s/u64/dma_addr_t/ ? I'm not sure what is the appropriate type,
just that this makes i915 not try and eat itself. :)
-Chris
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-22 16:08 ` Chris Wilson
0 siblings, 0 replies; 15+ messages in thread
From: Chris Wilson @ 2020-08-22 16:08 UTC (permalink / raw)
To: iommu; +Cc: intel-gfx, Joerg Roedel, stable
Quoting Chris Wilson (2020-08-22 17:02:09)
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
Maybe s/u64/dma_addr_t/ ? I'm not sure what is the appropriate type,
just that this makes i915 not try and eat itself. :)
-Chris
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
` (2 preceding siblings ...)
(?)
@ 2020-08-22 16:09 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-08-22 16:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: iommu/intel: Handle 36b addressing for x86-32
URL : https://patchwork.freedesktop.org/series/80918/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ce2e9f1b5e99 iommu/intel: Handle 36b addressing for x86-32
-:14: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")'
#14:
fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
total: 1 errors, 0 warnings, 0 checks, 36 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
` (3 preceding siblings ...)
(?)
@ 2020-08-22 16:26 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-08-22 16:26 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5726 bytes --]
== Series Details ==
Series: iommu/intel: Handle 36b addressing for x86-32
URL : https://patchwork.freedesktop.org/series/80918/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8914 -> Patchwork_18391
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/index.html
Known issues
------------
Here are the changes found in Patchwork_18391 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-byt-j1900/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_lrc:
- fi-tgl-u2: [PASS][7] -> [DMESG-FAIL][8] ([i915#2373])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][9] -> [DMESG-WARN][10] ([i915#2203])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-tgl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-tgl-u2/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-tgl-u2/igt@i915_module_load@reload.html
* igt@i915_selftest@live@gem_contexts:
- fi-tgl-u2: [INCOMPLETE][13] ([i915#2045]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-tgl-u2/igt@i915_selftest@live@gem_contexts.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#1982] / [i915#62] / [i915#92])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-kbl-x1275/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2045]: https://gitlab.freedesktop.org/drm/intel/issues/2045
[i915#2100]: https://gitlab.freedesktop.org/drm/intel/issues/2100
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (38 -> 34)
------------------------------
Missing (4): fi-byt-clapper fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
Build changes
-------------
* Linux: CI_DRM_8914 -> Patchwork_18391
CI-20190529: 20190529
CI_DRM_8914: 1339d80a19c0da27c443a4430fd0fe8a9d924b97 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5770: f1d0c240ea2e631dfb9f493f37f8fb61cb2b1cf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18391: ce2e9f1b5e99bc9b6dd1626f5741824a6d838750 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ce2e9f1b5e99 iommu/intel: Handle 36b addressing for x86-32
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/index.html
[-- Attachment #1.2: Type: text/html, Size: 7420 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
` (4 preceding siblings ...)
(?)
@ 2020-08-22 17:34 ` Patchwork
-1 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2020-08-22 17:34 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 13785 bytes --]
== Series Details ==
Series: iommu/intel: Handle 36b addressing for x86-32
URL : https://patchwork.freedesktop.org/series/80918/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8914_full -> Patchwork_18391_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18391_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18391_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18391_full:
### IGT changes ###
#### Possible regressions ####
* igt@perf@global-sseu-config:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl8/igt@perf@global-sseu-config.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl8/igt@perf@global-sseu-config.html
#### Warnings ####
* igt@runner@aborted:
- shard-skl: [FAIL][3] ([i915#2029]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl3/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl8/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_18391_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [PASS][5] -> [DMESG-FAIL][6] ([i915#118] / [i915#95]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-glk9/igt@kms_big_fb@linear-64bpp-rotate-180.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_color@pipe-b-ctm-negative:
- shard-skl: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl6/igt@kms_color@pipe-b-ctm-negative.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl7/igt@kms_color@pipe-b-ctm-negative.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [PASS][9] -> [DMESG-WARN][10] ([i915#1982]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][11] -> [FAIL][12] ([i915#1188])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl9/igt@kms_hdr@bpc-switch.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [i915#265]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@blocking-parameterized:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#1542])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-iclb5/igt@perf@blocking-parameterized.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-iclb8/igt@perf@blocking-parameterized.html
* igt@perf@polling-parameterized:
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#1542])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-kbl7/igt@perf@polling-parameterized.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-kbl4/igt@perf@polling-parameterized.html
* igt@prime_busy@hang@bcs0:
- shard-hsw: [PASS][23] -> [FAIL][24] ([i915#2258]) +4 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-hsw8/igt@prime_busy@hang@bcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-hsw6/igt@prime_busy@hang@bcs0.html
#### Possible fixes ####
* igt@gem_exec_balancer@bonded-early:
- shard-kbl: [FAIL][25] ([i915#2079]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-kbl2/igt@gem_exec_balancer@bonded-early.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-kbl2/igt@gem_exec_balancer@bonded-early.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-tglb: [INCOMPLETE][27] ([i915#1958]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-tglb8/igt@gem_exec_endless@dispatch@rcs0.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-tglb2/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_whisper@basic-forked:
- shard-glk: [DMESG-WARN][29] ([i915#118] / [i915#95]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-glk7/igt@gem_exec_whisper@basic-forked.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-glk9/igt@gem_exec_whisper@basic-forked.html
* igt@gem_flink_basic@basic:
- shard-snb: [TIMEOUT][31] ([i915#1958]) -> [PASS][32] +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-snb4/igt@gem_flink_basic@basic.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-snb4/igt@gem_flink_basic@basic.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-0:
- shard-glk: [DMESG-FAIL][33] ([i915#118] / [i915#95]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-glk2/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-apl: [DMESG-WARN][35] ([i915#1635] / [i915#1982]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-apl2/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-apl8/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][37] ([i915#2346]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][39] ([i915#180]) -> [PASS][40] +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-iclb: [DMESG-WARN][41] ([i915#1982]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][45] ([fdo#108145] / [i915#265]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48] +6 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][49] ([fdo#109441]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][51] ([i915#198]) -> [PASS][52] +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-skl10/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@polling-parameterized:
- shard-iclb: [FAIL][53] ([i915#1542]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-iclb6/igt@perf@polling-parameterized.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-iclb3/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_reloc@basic-concurrent16:
- shard-snb: [TIMEOUT][55] ([i915#1958]) -> [FAIL][56] ([i915#1930])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-snb4/igt@gem_exec_reloc@basic-concurrent16.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen:
- shard-snb: [TIMEOUT][57] ([i915#1958]) -> [SKIP][58] ([fdo#109271]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8914/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-64x21-onscreen.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079
[i915#2258]: https://gitlab.freedesktop.org/drm/intel/issues/2258
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8914 -> Patchwork_18391
CI-20190529: 20190529
CI_DRM_8914: 1339d80a19c0da27c443a4430fd0fe8a9d924b97 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5770: f1d0c240ea2e631dfb9f493f37f8fb61cb2b1cf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18391: ce2e9f1b5e99bc9b6dd1626f5741824a6d838750 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18391/index.html
[-- Attachment #1.2: Type: text/html, Size: 16311 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Intel-gfx] [PATCH] iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
(?)
@ 2020-08-25 3:13 ` Lu Baolu
-1 siblings, 0 replies; 15+ messages in thread
From: Lu Baolu @ 2020-08-25 3:13 UTC (permalink / raw)
To: Chris Wilson, iommu
Cc: James Sewart, intel-gfx, Joerg Roedel, stable, baolu.lu
Hi Chris,
On 2020/8/23 0:02, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
commit <fa954e683178> ("iommu/vt-d: Delegate the dma domain to upper layer")
and adjust the title as "iommu/vt-d: Handle 36bit addressing for x86-32"
with above two changes,
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards,
baolu
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
> {
> return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
> }
>
> -static inline unsigned long level_mask(int level)
> +static inline u64 level_mask(int level)
> {
> - return -1UL << level_to_offset_bits(level);
> + return -1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long level_size(int level)
> +static inline u64 level_size(int level)
> {
> - return 1UL << level_to_offset_bits(level);
> + return 1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long align_to_level(unsigned long pfn, int level)
> +static inline u64 align_to_level(u64 pfn, int level)
> {
> return (pfn + level_size(level) - 1) & level_mask(level);
> }
>
> static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
> {
> - return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> + return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> }
>
> /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-25 3:13 ` Lu Baolu
0 siblings, 0 replies; 15+ messages in thread
From: Lu Baolu @ 2020-08-25 3:13 UTC (permalink / raw)
To: Chris Wilson, iommu
Cc: baolu.lu, intel-gfx, James Sewart, Joerg Roedel, stable
Hi Chris,
On 2020/8/23 0:02, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
commit <fa954e683178> ("iommu/vt-d: Delegate the dma domain to upper layer")
and adjust the title as "iommu/vt-d: Handle 36bit addressing for x86-32"
with above two changes,
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards,
baolu
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
> {
> return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
> }
>
> -static inline unsigned long level_mask(int level)
> +static inline u64 level_mask(int level)
> {
> - return -1UL << level_to_offset_bits(level);
> + return -1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long level_size(int level)
> +static inline u64 level_size(int level)
> {
> - return 1UL << level_to_offset_bits(level);
> + return 1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long align_to_level(unsigned long pfn, int level)
> +static inline u64 align_to_level(u64 pfn, int level)
> {
> return (pfn + level_size(level) - 1) & level_mask(level);
> }
>
> static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
> {
> - return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> + return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> }
>
> /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-08-25 3:13 ` Lu Baolu
0 siblings, 0 replies; 15+ messages in thread
From: Lu Baolu @ 2020-08-25 3:13 UTC (permalink / raw)
To: Chris Wilson, iommu; +Cc: intel-gfx, Joerg Roedel, stable
Hi Chris,
On 2020/8/23 0:02, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
commit <fa954e683178> ("iommu/vt-d: Delegate the dma domain to upper layer")
and adjust the title as "iommu/vt-d: Handle 36bit addressing for x86-32"
with above two changes,
Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Best regards,
baolu
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e9c8c3d0da4..ba78a2e854f9 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -123,29 +123,29 @@ static inline unsigned int level_to_offset_bits(int level)
> return (level - 1) * LEVEL_STRIDE;
> }
>
> -static inline int pfn_level_offset(unsigned long pfn, int level)
> +static inline int pfn_level_offset(u64 pfn, int level)
> {
> return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
> }
>
> -static inline unsigned long level_mask(int level)
> +static inline u64 level_mask(int level)
> {
> - return -1UL << level_to_offset_bits(level);
> + return -1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long level_size(int level)
> +static inline u64 level_size(int level)
> {
> - return 1UL << level_to_offset_bits(level);
> + return 1ULL << level_to_offset_bits(level);
> }
>
> -static inline unsigned long align_to_level(unsigned long pfn, int level)
> +static inline u64 align_to_level(u64 pfn, int level)
> {
> return (pfn + level_size(level) - 1) & level_mask(level);
> }
>
> static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
> {
> - return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> + return 1UL << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
> }
>
> /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH] iommu/intel: Handle 36b addressing for x86-32
2020-08-22 16:02 ` Chris Wilson
(?)
@ 2020-09-04 10:14 ` Joerg Roedel
-1 siblings, 0 replies; 15+ messages in thread
From: Joerg Roedel @ 2020-09-04 10:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: James Sewart, iommu, intel-gfx, stable, Lu Baolu
On Sat, Aug 22, 2020 at 05:02:09PM +0100, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Applied for v5.9, thanks.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-09-04 10:14 ` Joerg Roedel
0 siblings, 0 replies; 15+ messages in thread
From: Joerg Roedel @ 2020-09-04 10:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: iommu, intel-gfx, James Sewart, Lu Baolu, stable
On Sat, Aug 22, 2020 at 05:02:09PM +0100, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Applied for v5.9, thanks.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH] iommu/intel: Handle 36b addressing for x86-32
@ 2020-09-04 10:14 ` Joerg Roedel
0 siblings, 0 replies; 15+ messages in thread
From: Joerg Roedel @ 2020-09-04 10:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: iommu, intel-gfx, stable
On Sat, Aug 22, 2020 at 05:02:09PM +0100, Chris Wilson wrote:
> Beware that the address size for x86-32 may exceed unsigned long.
>
> [ 0.368971] UBSAN: shift-out-of-bounds in drivers/iommu/intel/iommu.c:128:14
> [ 0.369055] shift exponent 36 is too large for 32-bit type 'long unsigned int'
>
> If we don't handle the wide addresses, the pages are mismapped and the
> device read/writes go astray, detected as DMAR faults and leading to
> device failure. The behaviour changed (from working to broken) in commit
> fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer"), but
> the error looks older.
>
> Fixes: fa954e683178 ("iommu/vt-d: Delegate the dma domain to upper layer")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: James Sewart <jamessewart@arista.com>
> Cc: Lu Baolu <baolu.lu@linux.intel.com>
> Cc: Joerg Roedel <jroedel@suse.de>
> Cc: <stable@vger.kernel.org> # v5.3+
> ---
> drivers/iommu/intel/iommu.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
Applied for v5.9, thanks.
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 15+ messages in thread