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From: Christoph Hellwig <hch@lst.de>
To: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
	Anup Patel <Anup.Patel@wdc.com>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>, Atish Patra <Atish.Patra@wdc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH] RISC-V: Allow drivers to provide custom read_cycles64 for M-mode kernel
Date: Mon, 7 Sep 2020 08:18:53 +0200	[thread overview]
Message-ID: <20200907061853.GA19038@lst.de> (raw)
In-Reply-To: <CAAhSdy3ESD6L_T1rFprDF2jduN8buTz173F6_mYCbTL3s4RG2A@mail.gmail.com>

On Sat, Sep 05, 2020 at 11:05:48AM +0530, Anup Patel wrote:
> Your patch will also break if the SOC specific timer has a 32bit
> free-running counter
> unlike the 64bit free-running counter found on CLINT.
> 
> I guess it's better to let the SOC timer driver provide the
> method/function to read the
> free-running counter.

Seriously, build the interfaces once you know the consumers.  Don't
build pie in the sky interfaces just because you can, because that
is what creates all the problems.

And of coruse at least for IPIs which absolutely are performance
criticical we need a standard interface (one that doesn't suck as much
as the SBI detour with the four extra context switches).  But I guess
I have already given up on RISC-V because the incompetency about things
like the irq design are just so horrible that it isn't worth bothering
any more.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
	Christoph Hellwig <hch@lst.de>, Anup Patel <Anup.Patel@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Atish Patra <Atish.Patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	Linus Torvalds <torvalds@linux-foundation.org>
Subject: Re: [PATCH] RISC-V: Allow drivers to provide custom read_cycles64 for M-mode kernel
Date: Mon, 7 Sep 2020 08:18:53 +0200	[thread overview]
Message-ID: <20200907061853.GA19038@lst.de> (raw)
In-Reply-To: <CAAhSdy3ESD6L_T1rFprDF2jduN8buTz173F6_mYCbTL3s4RG2A@mail.gmail.com>

On Sat, Sep 05, 2020 at 11:05:48AM +0530, Anup Patel wrote:
> Your patch will also break if the SOC specific timer has a 32bit
> free-running counter
> unlike the 64bit free-running counter found on CLINT.
> 
> I guess it's better to let the SOC timer driver provide the
> method/function to read the
> free-running counter.

Seriously, build the interfaces once you know the consumers.  Don't
build pie in the sky interfaces just because you can, because that
is what creates all the problems.

And of coruse at least for IPIs which absolutely are performance
criticical we need a standard interface (one that doesn't suck as much
as the SBI detour with the four extra context switches).  But I guess
I have already given up on RISC-V because the incompetency about things
like the irq design are just so horrible that it isn't worth bothering
any more.

  reply	other threads:[~2020-09-07  6:19 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 16:21 [PATCH] RISC-V: Allow drivers to provide custom read_cycles64 for M-mode kernel Anup Patel
2020-09-04 16:21 ` Anup Patel
2020-09-04 16:25 ` Christoph Hellwig
2020-09-04 16:25   ` Christoph Hellwig
2020-09-04 16:43   ` Anup Patel
2020-09-04 16:43     ` Anup Patel
2020-09-04 16:57     ` Christoph Hellwig
2020-09-04 16:57       ` Christoph Hellwig
2020-09-05  1:17       ` Palmer Dabbelt
2020-09-05  1:17         ` Palmer Dabbelt
2020-09-05  3:44         ` Anup Patel
2020-09-05  3:44           ` Anup Patel
2020-09-05  5:35           ` Anup Patel
2020-09-05  5:35             ` Anup Patel
2020-09-07  6:18             ` Christoph Hellwig [this message]
2020-09-07  6:18               ` Christoph Hellwig
2020-09-07  9:59               ` Anup Patel
2020-09-07  9:59                 ` Anup Patel

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