From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com, bp@alien8.de,
mchehab@kernel.org, tony.luck@intel.com, aou@eecs.berkeley.edu,
james.morse@arm.com, rrichter@marvell.com,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
sachin.ghadi@sifive.com
Subject: Re: [PATCH v2 0/3] SiFive DDR controller and EDAC support
Date: Tue, 15 Sep 2020 09:22:01 -0600 [thread overview]
Message-ID: <20200915152201.GA1940827@bogus> (raw)
In-Reply-To: <1599457679-8947-1-git-send-email-yash.shah@sifive.com>
On Mon, Sep 07, 2020 at 11:17:56AM +0530, Yash Shah wrote:
> The series add supports for SiFive DDR controller driver. This driver
> is use to manage the Cadence DDR controller present in SiFive SoCs.
> Currently it manages only the EDAC feature of the DDR controller.
> The series also adds Memory controller EDAC support for SiFive platform.
> It register for notifier event from SiFive DDR controller driver.
This is an odd split and notifiers aren't a great interface. Why not
just combine these? Is there some other DDR controller functionality
planned for the driver?
FYI, highbank_mc_edac.c is also a Cadence controller. IIRC, the register
layout changes for every customer/design.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: devicetree@vger.kernel.org, tony.luck@intel.com,
james.morse@arm.com, linux-kernel@vger.kernel.org,
rrichter@marvell.com, sachin.ghadi@sifive.com,
aou@eecs.berkeley.edu, bp@alien8.de, paul.walmsley@sifive.com,
palmer@dabbelt.com, linux-riscv@lists.infradead.org,
mchehab@kernel.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH v2 0/3] SiFive DDR controller and EDAC support
Date: Tue, 15 Sep 2020 09:22:01 -0600 [thread overview]
Message-ID: <20200915152201.GA1940827@bogus> (raw)
In-Reply-To: <1599457679-8947-1-git-send-email-yash.shah@sifive.com>
On Mon, Sep 07, 2020 at 11:17:56AM +0530, Yash Shah wrote:
> The series add supports for SiFive DDR controller driver. This driver
> is use to manage the Cadence DDR controller present in SiFive SoCs.
> Currently it manages only the EDAC feature of the DDR controller.
> The series also adds Memory controller EDAC support for SiFive platform.
> It register for notifier event from SiFive DDR controller driver.
This is an odd split and notifiers aren't a great interface. Why not
just combine these? Is there some other DDR controller functionality
planned for the driver?
FYI, highbank_mc_edac.c is also a Cadence controller. IIRC, the register
layout changes for every customer/design.
Rob
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http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-09-15 15:23 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 5:47 [PATCH v2 0/3] SiFive DDR controller and EDAC support Yash Shah
2020-09-07 5:47 ` Yash Shah
2020-09-07 5:47 ` [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-09-07 5:47 ` Yash Shah
2020-09-15 15:24 ` Rob Herring
2020-09-15 15:24 ` Rob Herring
2020-09-07 5:47 ` [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-09-07 5:47 ` Yash Shah
2020-09-07 5:54 ` Randy Dunlap
2020-09-07 5:54 ` Randy Dunlap
2020-09-07 6:11 ` Christoph Hellwig
2020-09-07 6:11 ` Christoph Hellwig
2020-09-09 3:12 ` Palmer Dabbelt
2020-09-09 3:12 ` Palmer Dabbelt
2020-09-09 3:56 ` Yash Shah
2020-09-09 3:56 ` Yash Shah
2020-09-09 6:00 ` Christoph Hellwig
2020-09-09 6:00 ` Christoph Hellwig
2020-09-09 20:31 ` Palmer Dabbelt
2020-09-09 20:31 ` Palmer Dabbelt
2020-09-17 9:56 ` Dhananjay Vilasrao Kangude
2020-09-17 9:56 ` Dhananjay Vilasrao Kangude
2020-09-07 5:47 ` [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-09-07 5:47 ` Yash Shah
2020-09-23 17:10 ` Borislav Petkov
2020-09-23 17:10 ` Borislav Petkov
2020-09-15 15:22 ` Rob Herring [this message]
2020-09-15 15:22 ` [PATCH v2 0/3] SiFive DDR controller and EDAC support Rob Herring
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