From: Rob Herring <robh@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-edac@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
Robert Richter <rrichter@marvell.com>,
Borislav Petkov <bp@alien8.de>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
York Sun <york.sun@nxp.com>, Rob Herring <robh+dt@kernel.org>,
kernel@pengutronix.de, James Morse <james.morse@arm.com>
Subject: Re: [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57
Date: Wed, 14 Oct 2020 08:25:36 -0500 [thread overview]
Message-ID: <20201014132536.GA1535030@bogus> (raw)
In-Reply-To: <20201013125033.4749-2-s.hauer@pengutronix.de>
On Tue, 13 Oct 2020 14:50:31 +0200, Sascha Hauer wrote:
> The ARM Cortex-A53 and A57 CPUs support error detection for the L1/L2
> caches. This patch adds a binding for the corresponding driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> .../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: 'maintainers' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
See https://patchwork.ozlabs.org/patch/1381567
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: devicetree@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
Rob Herring <robh+dt@kernel.org>,
Robert Richter <rrichter@marvell.com>,
Borislav Petkov <bp@alien8.de>,
kernel@pengutronix.de, James Morse <james.morse@arm.com>,
York Sun <york.sun@nxp.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57
Date: Wed, 14 Oct 2020 08:25:36 -0500 [thread overview]
Message-ID: <20201014132536.GA1535030@bogus> (raw)
In-Reply-To: <20201013125033.4749-2-s.hauer@pengutronix.de>
On Tue, 13 Oct 2020 14:50:31 +0200, Sascha Hauer wrote:
> The ARM Cortex-A53 and A57 CPUs support error detection for the L1/L2
> caches. This patch adds a binding for the corresponding driver.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> .../bindings/edac/arm,cortex-a5x-edac.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: 'maintainers' is a required property
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml: ignoring, error in schema:
warning: no schema found in file: ./Documentation/devicetree/bindings/edac/arm,cortex-a5x-edac.yaml
See https://patchwork.ozlabs.org/patch/1381567
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-10-14 13:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 12:50 [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-10-13 12:50 ` Sascha Hauer
2020-10-13 12:50 ` [PATCH 1/3] dt-bindings: edac: Add binding for L1/L2 error detection for Cortex A53/57 Sascha Hauer
2020-10-13 12:50 ` Sascha Hauer
2020-10-14 13:25 ` Rob Herring [this message]
2020-10-14 13:25 ` Rob Herring
2020-10-13 12:50 ` [PATCH 2/3] drivers/edac: Add L1 and L2 error detection for A53 and A57 Sascha Hauer
2020-10-13 12:50 ` Sascha Hauer
2020-11-06 19:34 ` James Morse
2020-11-06 19:34 ` James Morse
2020-10-13 12:50 ` [PATCH 3/3] arm64: dts: ls104x: Add L1/L2 cache edac node Sascha Hauer
2020-10-13 12:50 ` Sascha Hauer
2020-10-14 13:25 ` [PATCH v2 0/3] Add L1 and L2 error detection for A53 and A57 Rob Herring
2020-10-14 13:25 ` Rob Herring
2020-10-14 14:04 ` Sascha Hauer
2020-10-14 14:04 ` Sascha Hauer
2020-10-14 15:17 ` Rob Herring
2020-10-14 15:17 ` Rob Herring
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