[Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers

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* [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers
@ 2020-10-23 13:34 Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/ Ville Syrjala
                   ` (22 more replies)
  0 siblings, 23 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remainder of the latest hpd cleanup. Apart from rebasing I
didn't change much, except I did the s/TC_PORT_TC1/TC_PORT_1/
thing Lucas suggested.

Ville Syrjälä (19):
  drm/i915: s/PORT_TC/TC_PORT_/
  drm/i915: Add PORT_TCn aliases to enum port
  drm/i915: Give DDI encoders even better names
  drm/i915: Introduce AUX_CH_USBCn
  drm/i915: Pimp AUX CH names
  drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
  drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
  drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
  drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
  drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()
  drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
  drm/i915: Relocate intel_hpd_{enabled,hotplug}_irqs()
  drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
  drm/i915: Don't enable hpd detection logic from irq_postinstall()
  drm/i915: Rename 'tmp_mask'
  drm/i915: Remove the per-plaform IIR HPD masking
  drm/i915: Enable hpd logic only for ports that are present
  drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
  drm/i915: Get rid of ibx_irq_pre_postinstall()

 drivers/gpu/drm/i915/display/intel_bios.c    |  18 +-
 drivers/gpu/drm/i915/display/intel_ddi.c     |  31 +-
 drivers/gpu/drm/i915/display/intel_display.c |  30 +-
 drivers/gpu/drm/i915/display/intel_display.h |  30 +-
 drivers/gpu/drm/i915/display/intel_dp.c      |  66 ++-
 drivers/gpu/drm/i915/display/intel_tc.c      |   2 +-
 drivers/gpu/drm/i915/gvt/display.c           |  15 +-
 drivers/gpu/drm/i915/i915_irq.c              | 549 ++++++++++---------
 drivers/gpu/drm/i915/i915_reg.h              | 114 ++--
 9 files changed, 493 insertions(+), 362 deletions(-)

-- 
2.26.2

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^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 17:57   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
                   ` (21 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Make the namespacing for enum tc_port better by adding
the TC_ to the actual enum values.

v2: Drop the extra TC (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
 drivers/gpu/drm/i915/display/intel_tc.c      |  2 +-
 drivers/gpu/drm/i915/i915_irq.c              | 78 ++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h              | 60 +++++++--------
 5 files changed, 78 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f41b6f8b5618..da2a91122d44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7474,7 +7474,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
 	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
-		return PORT_TC_NONE;
+		return TC_PORT_NONE;
 
 	if (INTEL_GEN(dev_priv) >= 12)
 		return port - PORT_D;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b946209e06b..1b7ae1d507f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -244,14 +244,14 @@ static inline const char *port_identifier(enum port port)
 }
 
 enum tc_port {
-	PORT_TC_NONE = -1,
+	TC_PORT_NONE = -1,
 
-	PORT_TC1 = 0,
-	PORT_TC2,
-	PORT_TC3,
-	PORT_TC4,
-	PORT_TC5,
-	PORT_TC6,
+	TC_PORT_1 = 0,
+	TC_PORT_2,
+	TC_PORT_3,
+	TC_PORT_4,
+	TC_PORT_5,
+	TC_PORT_6,
 
 	I915_MAX_TC_PORTS
 };
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 8f67aef18b2d..1cb548d757e1 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 	enum port port = dig_port->base.port;
 	enum tc_port tc_port = intel_port_to_tc(i915, port);
 
-	if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
+	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
 		return;
 
 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 53e67c796d09..fd65d1c9a4d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1032,17 +1032,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
 	case HPD_PORT_TC2:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
 	case HPD_PORT_TC3:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
 	case HPD_PORT_TC4:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
 	case HPD_PORT_TC5:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
 	case HPD_PORT_TC6:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
 	default:
 		return false;
 	}
@@ -1080,17 +1080,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
 	case HPD_PORT_TC2:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
 	case HPD_PORT_TC3:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
 	case HPD_PORT_TC4:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
 	case HPD_PORT_TC5:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
 	case HPD_PORT_TC6:
-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
 	default:
 		return false;
 	}
@@ -1869,7 +1869,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		tc_hotplug_trigger = 0;
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
 	} else {
 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
 			 "Unrecognized PCH type 0x%x\n",
@@ -3237,7 +3237,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
 }
 
 /*
@@ -3256,21 +3256,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3643,7 +3643,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
 	} else {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4952c9875fb..0d43ae262606 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7891,19 +7891,19 @@ enum {
 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
 #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(PORT_TC6) | \
-						 GEN11_TC_HOTPLUG(PORT_TC5) | \
-						 GEN11_TC_HOTPLUG(PORT_TC4) | \
-						 GEN11_TC_HOTPLUG(PORT_TC3) | \
-						 GEN11_TC_HOTPLUG(PORT_TC2) | \
-						 GEN11_TC_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
+						 GEN11_TC_HOTPLUG(TC_PORT_1))
 #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(PORT_TC6) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC5) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC4) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC3) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC2) | \
-						 GEN11_TBT_HOTPLUG(PORT_TC1))
+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
+						 GEN11_TBT_HOTPLUG(TC_PORT_1))
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
@@ -8352,19 +8352,19 @@ enum {
 #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
 #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8449,15 +8449,15 @@ enum {
 
 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC1))
+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_1))
 #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
+					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 
 #define _PCH_DPLL_A              0xc6014
@@ -10315,9 +10315,9 @@ enum skl_power_gate {
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
-						       (tc_port) - PORT_TC4 + 21))
+						       (tc_port) - TC_PORT_4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-- 
2.26.2

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^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/ Ville Syrjala
@ 2020-10-23 17:57   ` Lucas De Marchi
  2020-10-23 18:08     ` Ville Syrjälä
  0 siblings, 1 reply; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 17:57 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:02PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Make the namespacing for enum tc_port better by adding
>the TC_ to the actual enum values.
>
>v2: Drop the extra TC (Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c |  2 +-
> drivers/gpu/drm/i915/display/intel_display.h | 14 ++--
> drivers/gpu/drm/i915/display/intel_tc.c      |  2 +-
> drivers/gpu/drm/i915/i915_irq.c              | 78 ++++++++++----------
> drivers/gpu/drm/i915/i915_reg.h              | 60 +++++++--------
> 5 files changed, 78 insertions(+), 78 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index f41b6f8b5618..da2a91122d44 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -7474,7 +7474,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> {
> 	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>-		return PORT_TC_NONE;
>+		return TC_PORT_NONE;
>
> 	if (INTEL_GEN(dev_priv) >= 12)
> 		return port - PORT_D;
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index 1b946209e06b..1b7ae1d507f2 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -244,14 +244,14 @@ static inline const char *port_identifier(enum port port)
> }
>
> enum tc_port {
>-	PORT_TC_NONE = -1,
>+	TC_PORT_NONE = -1,
>
>-	PORT_TC1 = 0,
>-	PORT_TC2,
>-	PORT_TC3,
>-	PORT_TC4,
>-	PORT_TC5,
>-	PORT_TC6,
>+	TC_PORT_1 = 0,
>+	TC_PORT_2,
>+	TC_PORT_3,
>+	TC_PORT_4,
>+	TC_PORT_5,
>+	TC_PORT_6,
>
> 	I915_MAX_TC_PORTS
> };
>diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>index 8f67aef18b2d..1cb548d757e1 100644
>--- a/drivers/gpu/drm/i915/display/intel_tc.c
>+++ b/drivers/gpu/drm/i915/display/intel_tc.c
>@@ -652,7 +652,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
> 	enum port port = dig_port->base.port;
> 	enum tc_port tc_port = intel_port_to_tc(i915, port);
>
>-	if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE))
>+	if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
> 		return;
>
> 	snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 53e67c796d09..fd65d1c9a4d2 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -132,24 +132,24 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_gen11[HPD_NUM_PINS] = {
>-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(PORT_TC1) | GEN11_TBT_HOTPLUG(PORT_TC1),
>-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(PORT_TC2) | GEN11_TBT_HOTPLUG(PORT_TC2),
>-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(PORT_TC3) | GEN11_TBT_HOTPLUG(PORT_TC3),
>-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(PORT_TC4) | GEN11_TBT_HOTPLUG(PORT_TC4),
>-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(PORT_TC5) | GEN11_TBT_HOTPLUG(PORT_TC5),
>-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(PORT_TC6) | GEN11_TBT_HOTPLUG(PORT_TC6),
>+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
>+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
>+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
>+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
>+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
>+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
> 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
> 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
> 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
>-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
>-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
>-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
>-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
>-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
>-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
>+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
>+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
>+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
>+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
>+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
>+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
> };
>
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>@@ -1032,17 +1032,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> 	switch (pin) {
> 	case HPD_PORT_TC1:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
> 	case HPD_PORT_TC2:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
> 	case HPD_PORT_TC3:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
> 	case HPD_PORT_TC4:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
> 	case HPD_PORT_TC5:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
> 	case HPD_PORT_TC6:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
> 	default:
> 		return false;
> 	}
>@@ -1080,17 +1080,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> 	switch (pin) {
> 	case HPD_PORT_TC1:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
> 	case HPD_PORT_TC2:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
> 	case HPD_PORT_TC3:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
> 	case HPD_PORT_TC4:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
> 	case HPD_PORT_TC5:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
> 	case HPD_PORT_TC6:
>-		return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
>+		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
> 	default:
> 		return false;
> 	}
>@@ -1869,7 +1869,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> 		tc_hotplug_trigger = 0;
> 	} else if (HAS_PCH_MCC(dev_priv)) {
> 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
>+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
> 	} else {
> 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
> 			 "Unrecognized PCH type 0x%x\n",
>@@ -3237,7 +3237,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
> static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> 	icp_hpd_irq_setup(dev_priv,
>-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
>+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
> }
>
> /*
>@@ -3256,21 +3256,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	u32 hotplug;
>
> 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
>+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
> 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
>
> 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(PORT_TC6);
>+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
> 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
> }
>
>@@ -3643,7 +3643,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> 	} else if (HAS_PCH_MCC(dev_priv)) {
> 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
>-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(PORT_TC1));
>+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
> 	} else {
> 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index d4952c9875fb..0d43ae262606 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7891,19 +7891,19 @@ enum {
> #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
> #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
> #define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
>-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(PORT_TC6) | \
>-						 GEN11_TC_HOTPLUG(PORT_TC5) | \
>-						 GEN11_TC_HOTPLUG(PORT_TC4) | \
>-						 GEN11_TC_HOTPLUG(PORT_TC3) | \
>-						 GEN11_TC_HOTPLUG(PORT_TC2) | \
>-						 GEN11_TC_HOTPLUG(PORT_TC1))
>+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
>+						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
>+						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
>+						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
>+						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
>+						 GEN11_TC_HOTPLUG(TC_PORT_1))
> #define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
>-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(PORT_TC6) | \
>-						 GEN11_TBT_HOTPLUG(PORT_TC5) | \
>-						 GEN11_TBT_HOTPLUG(PORT_TC4) | \
>-						 GEN11_TBT_HOTPLUG(PORT_TC3) | \
>-						 GEN11_TBT_HOTPLUG(PORT_TC2) | \
>-						 GEN11_TBT_HOTPLUG(PORT_TC1))
>+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
>+						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
>+						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
>+						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
>+						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
>+						 GEN11_TBT_HOTPLUG(TC_PORT_1))
>
> #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
> #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
>@@ -8352,19 +8352,19 @@ enum {
> #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
> #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
>-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))

At some point we may also want to add *HOTPLUG* to these macros to
signify what it really is.  For another day.


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
>-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
>-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
>+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
>+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
>
> #define SDEISR  _MMIO(0xc4000)
> #define SDEIMR  _MMIO(0xc4004)
>@@ -8449,15 +8449,15 @@ enum {
>
> #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
>-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
>-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
>-					 ICP_TC_HPD_ENABLE(PORT_TC1))
>+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
>+					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
>+					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
>+					 ICP_TC_HPD_ENABLE(TC_PORT_1))
> #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
>-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
>-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
>+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
>+					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
> 					 ICP_TC_HPD_ENABLE_MASK)
>
> #define _PCH_DPLL_A              0xc6014
>@@ -10315,9 +10315,9 @@ enum skl_power_gate {
> #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
> #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
> #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
>-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
>+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
> 						       (tc_port) + 12 : \
>-						       (tc_port) - PORT_TC4 + 21))
>+						       (tc_port) - TC_PORT_4 + 21))
> #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
> #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>-- 
>2.26.2
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/
  2020-10-23 17:57   ` Lucas De Marchi
@ 2020-10-23 18:08     ` Ville Syrjälä
  0 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjälä @ 2020-10-23 18:08 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 10:57:24AM -0700, Lucas De Marchi wrote:
> On Fri, Oct 23, 2020 at 04:34:02PM +0300, Ville Syrjälä wrote:
> >@@ -8352,19 +8352,19 @@ enum {
> > #define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
> > #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
> >-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
> >+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
> 
> At some point we may also want to add *HOTPLUG* to these macros to
> signify what it really is.  For another day.

Hmm. I have a feeling I end up removing these before the end of the
series. Ah no, that was in a followup patch I played around with.
But I'm not convinced that patch (making the IIR readout mask
calculation also based on the encoders present) is actually a
necessary thing. I guess it would be if some if the hpd bits get
repurposed and we still want to share the irq handler between
platforms with conflicting bits.

> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Lucas De Marchi
> 
> > #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
> > 					 SDE_DDI_HOTPLUG_ICP(PORT_A))
> >-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(PORT_TC6) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC5) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC4) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
> >-					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
> >+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
> >+					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
> >
> > #define SDEISR  _MMIO(0xc4000)
> > #define SDEIMR  _MMIO(0xc4004)
> >@@ -8449,15 +8449,15 @@ enum {
> >
> > #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> >-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC4) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC3) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC2) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC1))
> >+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_1))
> > #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
> > 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
> >-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
> >-					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
> >+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
> >+					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
> > 					 ICP_TC_HPD_ENABLE_MASK)
> >
> > #define _PCH_DPLL_A              0xc6014
> >@@ -10315,9 +10315,9 @@ enum skl_power_gate {
> > #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
> > #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
> >-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
> >+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
> > 						       (tc_port) + 12 : \
> >-						       (tc_port) - PORT_TC4 + 21))
> >+						       (tc_port) - TC_PORT_4 + 21))
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> > #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> >-- 
> >2.26.2
> >

-- 
Ville Syrjälä
Intel
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/ Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:02   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 03/19] drm/i915: Give DDI encoders even better names Ville Syrjala
                   ` (20 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
Add the appropriate enum values for the TC DDIs to enum port.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c    | 10 +++----
 drivers/gpu/drm/i915/display/intel_ddi.c     |  4 +--
 drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++
 4 files changed, 28 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0a309645fe06..ff825be0ac88 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1688,17 +1688,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
 	};
 	/*
-	 * Bspec lists the ports as A, B, C, D - however internally in our
-	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
-	 * registers in Display Engine match the right offsets. Apply the
-	 * mapping here to translate from VBT to internal convention.
+	 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
+	 * map to DDI A,B,TC1,TC2 respectively.
 	 */
 	static const int rkl_port_mapping[][3] = {
 		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
 		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
 		[PORT_C] = { -1 },
-		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
-		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
+		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
+		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
 
 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..cf157e8f68cb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5069,8 +5069,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
 				enum port port)
 {
-	if (port >= PORT_D)
-		return HPD_PORT_TC1 + port - PORT_D;
+	if (port >= PORT_TC1)
+		return HPD_PORT_TC1 + port - PORT_TC1;
 	else
 		return HPD_PORT_A + port - PORT_A;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index da2a91122d44..cddbda5303ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7463,12 +7463,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
-		return (enum phy)port - 1;
+	if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
+		return PHY_C + port - PORT_TC1;
 	else if (IS_JSL_EHL(i915) && port == PORT_D)
 		return PHY_A;
 
-	return (enum phy)port;
+	return PHY_A + port - PORT_A;
 }
 
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
@@ -7477,9 +7477,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 		return TC_PORT_NONE;
 
 	if (INTEL_GEN(dev_priv) >= 12)
-		return port - PORT_D;
-
-	return port - PORT_C;
+		return TC_PORT_1 + port - PORT_TC1;
+	else
+		return TC_PORT_1 + port - PORT_C;
 }
 
 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
@@ -17216,17 +17216,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_D);
-		intel_ddi_init(dev_priv, PORT_E);
-		intel_ddi_init(dev_priv, PORT_F);
-		intel_ddi_init(dev_priv, PORT_G);
-		intel_ddi_init(dev_priv, PORT_H);
-		intel_ddi_init(dev_priv, PORT_I);
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC4);
+		intel_ddi_init(dev_priv, PORT_TC5);
+		intel_ddi_init(dev_priv, PORT_TC6);
 		icl_dsi_init(dev_priv);
 	} else if (IS_JSL_EHL(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 1b7ae1d507f2..747aec8e8580 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -208,6 +208,14 @@ enum port {
 	PORT_H,
 	PORT_I,
 
+	/* tgl+ */
+	PORT_TC1 = PORT_D,
+	PORT_TC2,
+	PORT_TC3,
+	PORT_TC4,
+	PORT_TC5,
+	PORT_TC6,
+
 	I915_MAX_PORTS
 };
 
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
@ 2020-10-23 19:02   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:02 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:03PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Since tgl the DDIs have been named A,B,C,TC1,TC2,TC3...
>Add the appropriate enum values for the TC DDIs to enum port.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_bios.c    | 10 +++----
> drivers/gpu/drm/i915/display/intel_ddi.c     |  4 +--
> drivers/gpu/drm/i915/display/intel_display.c | 28 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_display.h |  8 ++++++
> 4 files changed, 28 insertions(+), 22 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>index 0a309645fe06..ff825be0ac88 100644
>--- a/drivers/gpu/drm/i915/display/intel_bios.c
>+++ b/drivers/gpu/drm/i915/display/intel_bios.c
>@@ -1688,17 +1688,15 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
> 		[PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 },
> 	};
> 	/*
>-	 * Bspec lists the ports as A, B, C, D - however internally in our
>-	 * driver we keep them as PORT_A, PORT_B, PORT_D and PORT_E so the
>-	 * registers in Display Engine match the right offsets. Apply the
>-	 * mapping here to translate from VBT to internal convention.
>+	 * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D
>+	 * map to DDI A,B,TC1,TC2 respectively.
> 	 */
> 	static const int rkl_port_mapping[][3] = {
> 		[PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 },
> 		[PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 },
> 		[PORT_C] = { -1 },
>-		[PORT_D] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
>-		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
>+		[PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 },
>+		[PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
> 	};
>
> 	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 09811be08cfe..cf157e8f68cb 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -5069,8 +5069,8 @@ static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
> static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
> 				enum port port)
> {
>-	if (port >= PORT_D)
>-		return HPD_PORT_TC1 + port - PORT_D;
>+	if (port >= PORT_TC1)
>+		return HPD_PORT_TC1 + port - PORT_TC1;
> 	else
> 		return HPD_PORT_A + port - PORT_A;
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index da2a91122d44..cddbda5303ff 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -7463,12 +7463,12 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> {
>-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
>-		return (enum phy)port - 1;
>+	if (IS_ROCKETLAKE(i915) && port >= PORT_TC1)
>+		return PHY_C + port - PORT_TC1;
> 	else if (IS_JSL_EHL(i915) && port == PORT_D)
> 		return PHY_A;
>
>-	return (enum phy)port;
>+	return PHY_A + port - PORT_A;
> }
>
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>@@ -7477,9 +7477,9 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> 		return TC_PORT_NONE;
>
> 	if (INTEL_GEN(dev_priv) >= 12)
>-		return port - PORT_D;
>-
>-	return port - PORT_C;
>+		return TC_PORT_1 + port - PORT_TC1;
>+	else
>+		return TC_PORT_1 + port - PORT_C;
> }
>
> enum intel_display_power_domain intel_port_to_power_domain(enum port port)
>@@ -17216,17 +17216,17 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> 	if (IS_ROCKETLAKE(dev_priv)) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
>-		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
>-		intel_ddi_init(dev_priv, PORT_E);	/* DDI TC2 */
>+		intel_ddi_init(dev_priv, PORT_TC1);
>+		intel_ddi_init(dev_priv, PORT_TC2);
> 	} else if (INTEL_GEN(dev_priv) >= 12) {
> 		intel_ddi_init(dev_priv, PORT_A);
> 		intel_ddi_init(dev_priv, PORT_B);
>-		intel_ddi_init(dev_priv, PORT_D);
>-		intel_ddi_init(dev_priv, PORT_E);
>-		intel_ddi_init(dev_priv, PORT_F);
>-		intel_ddi_init(dev_priv, PORT_G);
>-		intel_ddi_init(dev_priv, PORT_H);
>-		intel_ddi_init(dev_priv, PORT_I);
>+		intel_ddi_init(dev_priv, PORT_TC1);
>+		intel_ddi_init(dev_priv, PORT_TC2);
>+		intel_ddi_init(dev_priv, PORT_TC2);
>+		intel_ddi_init(dev_priv, PORT_TC4);
>+		intel_ddi_init(dev_priv, PORT_TC5);
>+		intel_ddi_init(dev_priv, PORT_TC6);
> 		icl_dsi_init(dev_priv);
> 	} else if (IS_JSL_EHL(dev_priv)) {
> 		intel_ddi_init(dev_priv, PORT_A);
>diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>index 1b7ae1d507f2..747aec8e8580 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.h
>+++ b/drivers/gpu/drm/i915/display/intel_display.h
>@@ -208,6 +208,14 @@ enum port {
> 	PORT_H,
> 	PORT_I,
>
>+	/* tgl+ */
>+	PORT_TC1 = PORT_D,
>+	PORT_TC2,
>+	PORT_TC3,
>+	PORT_TC4,
>+	PORT_TC5,
>+	PORT_TC6,
>+
> 	I915_MAX_PORTS
> };
>
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 03/19] drm/i915: Give DDI encoders even better names
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/ Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 04/19] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
                   ` (19 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's pimp the DDI encoder->name to reflect what the spec calls them.
Ie. on pre-tgl DDI A-F, on tgl+ DDI A-C or DDI TC1-6.

Also since each encoder is really a combination of the DDI and the PHY
we include the PHY name as well.

ICL is a bit special since it already has the two different types
of DDIs (combo or TC) but it still calls them just DDI A-F regarless
of the type. For that let's add an extra "(TC)" note to remind
is which type of DDI it really is.

The code is darn ugly, but not sure there's much we can do about it.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 27 ++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cf157e8f68cb..5eab0cb3503e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5165,8 +5165,31 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	encoder = &dig_port->base;
 
-	drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
-			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
+	if (INTEL_GEN(dev_priv) >= 12) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %s%c/PHY %s%c",
+				 port >= PORT_TC1 ? "TC" : "",
+				 port >= PORT_TC1 ? port_name(port) : port - PORT_TC1 + '1',
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c%s/PHY %s%c",
+				 port_name(port),
+				 port >= PORT_C ? " (TC)" : "",
+				 tc_port != TC_PORT_NONE ? "TC" : "",
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');
+	} else {
+		drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+				 DRM_MODE_ENCODER_TMDS,
+				 "DDI %c/PHY %c", port_name(port),  phy_name(phy));
+	}
 
 	mutex_init(&dig_port->hdcp_mutex);
 	dig_port->num_hdcp_streams = 0;
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 04/19] drm/i915: Introduce AUX_CH_USBCn
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (2 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 03/19] drm/i915: Give DDI encoders even better names Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 05/19] drm/i915: Pimp AUX CH names Ville Syrjala
                   ` (18 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just like with the DDIs tgl+ renamed the AUX CHs to reflect
the type of the DDI. Let's add the aliasing enum values for
the type-C AUX CHs.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.h |  8 +++
 drivers/gpu/drm/i915/display/intel_dp.c      | 53 ++++++++++++++++++--
 2 files changed, 58 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 747aec8e8580..be774f216065 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -291,6 +291,14 @@ enum aux_ch {
 	AUX_CH_G,
 	AUX_CH_H,
 	AUX_CH_I,
+
+	/* tgl+ */
+	AUX_CH_USBC1 = AUX_CH_D,
+	AUX_CH_USBC2,
+	AUX_CH_USBC3,
+	AUX_CH_USBC4,
+	AUX_CH_USBC5,
+	AUX_CH_USBC6,
 };
 
 #define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 818daab252f3..b4f824383fe0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1774,7 +1774,6 @@ static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
 		return DP_AUX_CH_CTL(aux_ch);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1795,7 +1794,52 @@ static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
 	case AUX_CH_D:
 	case AUX_CH_E:
 	case AUX_CH_F:
-	case AUX_CH_G:
+		return DP_AUX_CH_DATA(aux_ch, index);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_DATA(AUX_CH_A, index);
+	}
+}
+
+static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
+		return DP_AUX_CH_CTL(aux_ch);
+	default:
+		MISSING_CASE(aux_ch);
+		return DP_AUX_CH_CTL(AUX_CH_A);
+	}
+}
+
+static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum aux_ch aux_ch = dig_port->aux_ch;
+
+	switch (aux_ch) {
+	case AUX_CH_A:
+	case AUX_CH_B:
+	case AUX_CH_C:
+	case AUX_CH_USBC1:
+	case AUX_CH_USBC2:
+	case AUX_CH_USBC3:
+	case AUX_CH_USBC4:
+	case AUX_CH_USBC5:
+	case AUX_CH_USBC6:
 		return DP_AUX_CH_DATA(aux_ch, index);
 	default:
 		MISSING_CASE(aux_ch);
@@ -1816,7 +1860,10 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 12) {
+		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
+		intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
+	} else if (INTEL_GEN(dev_priv) >= 9) {
 		intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
 		intel_dp->aux_ch_data_reg = skl_aux_data_reg;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 05/19] drm/i915: Pimp AUX CH names
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (3 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 04/19] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
                   ` (17 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's make the AUX CH names match the spec (AUX A-F for pre-tgl,
AUX A-C or AUX USBC1-6 for tgl+). And while at it let's include
the full encoder name in the AUX CH name as well (as opposed to
just using port_name() which wouldn't give us the right thing on
tgl+).

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b4f824383fe0..cf09aca7607b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1859,6 +1859,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
+	enum aux_ch aux_ch = dig_port->aux_ch;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
@@ -1891,9 +1892,15 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
 	drm_dp_aux_init(&intel_dp->aux);
 
 	/* Failure to allocate our preferred name is not critical */
-	intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c",
-				       aux_ch_name(dig_port->aux_ch),
-				       port_name(encoder->port));
+	if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
+					       aux_ch - AUX_CH_USBC1 + '1',
+					       encoder->base.name);
+	else
+		intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+					       aux_ch_name(aux_ch),
+					       encoder->base.name);
+
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
 }
 
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (4 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 05/19] drm/i915: Pimp AUX CH names Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
                   ` (16 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

As with the VBT DVO port, RKL uses PHY based mapping for the
VBT AUX CH. Adjust the code to use the new AUX_USBCn names
and add a comment to explain the situation.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index ff825be0ac88..4cc949b228f2 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2664,12 +2664,16 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
+		/*
+		 * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D
+		 * map to DDI A,B,TC1,TC2 respectively.
+		 */
 		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_D : AUX_CH_C;
+			AUX_CH_USBC1 : AUX_CH_C;
 		break;
 	case DP_AUX_D:
 		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
-			AUX_CH_E : AUX_CH_D;
+			AUX_CH_USBC2 : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (5 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
                   ` (15 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin to parametrize BXT_DE_PORT_HP_DDI() to make it clear
these have nothing to do with DDI ports or PHYs as such. The only
thing that matters is the HPD pin assignment.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/display.c | 13 +++++++------
 drivers/gpu/drm/i915/i915_irq.c    | 12 ++++++------
 drivers/gpu/drm/i915/i915_reg.h    | 12 ++++++------
 3 files changed, 19 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 7ba16ddfe75f..c124734e114c 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -173,23 +173,24 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	int pipe;
 
 	if (IS_BROXTON(dev_priv)) {
-		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
-			BXT_DE_PORT_HP_DDIB |
-			BXT_DE_PORT_HP_DDIC);
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
+			~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
+			  BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
+			  BXT_DE_PORT_HP_DDI(HPD_PORT_C));
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIA;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_A);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIB;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_B);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDIC;
+				BXT_DE_PORT_HP_DDI(HPD_PORT_C);
 		}
 
 		return;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fd65d1c9a4d2..991384f96faa 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
-	[HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
-	[HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
+	[HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
+	[HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
+	[HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -3390,13 +3390,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	 * For BXT invert bit has to be set based on AOB design
 	 * for HPD detection logic, update it based on VBT fields.
 	 */
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
 		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
 		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
+	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
 		hotplug |= BXT_DDIC_HPD_INVERT;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d43ae262606..4ab570809d58 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7812,6 +7812,8 @@ enum {
 	(GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
 	 GEN11_PIPE_PLANE5_FAULT)
 
+#define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
+
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
@@ -7825,12 +7827,10 @@ enum {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
-#define  BXT_DE_PORT_HP_DDIC		(1 << 5)
-#define  BXT_DE_PORT_HP_DDIB		(1 << 4)
-#define  BXT_DE_PORT_HP_DDIA		(1 << 3)
-#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDIA | \
-					 BXT_DE_PORT_HP_DDIB | \
-					 BXT_DE_PORT_HP_DDIC)
+#define  BXT_DE_PORT_HP_DDI(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
+					 BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
+					 BXT_DE_PORT_HP_DDI(HPD_PORT_C))
 #define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (6 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
                   ` (14 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Unify the BDW/BXT hotplug bits. BDW only has port A, but that
matches BXT port A so we can shar the same macro for both.

v2: Remember the gvt

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gvt/display.c | 14 +++++++-------
 drivers/gpu/drm/i915/i915_irq.c    | 18 +++++++++---------
 drivers/gpu/drm/i915/i915_reg.h    | 10 +++++-----
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index c124734e114c..5b5c71a0b4af 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -174,23 +174,23 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 
 	if (IS_BROXTON(dev_priv)) {
 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
-			~(BXT_DE_PORT_HP_DDI(HPD_PORT_A) |
-			  BXT_DE_PORT_HP_DDI(HPD_PORT_B) |
-			  BXT_DE_PORT_HP_DDI(HPD_PORT_C));
+			~(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) |
+			  GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_A);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_B);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_B);
 		}
 
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				BXT_DE_PORT_HP_DDI(HPD_PORT_C);
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_C);
 		}
 
 		return;
@@ -328,7 +328,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 		if (IS_BROADWELL(dev_priv))
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
-				GEN8_PORT_DP_A_HOTPLUG;
+				GEN8_DE_PORT_HOTPLUG(HPD_PORT_A);
 		else
 			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 991384f96faa..c84b6a0a17a2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -71,7 +71,7 @@ static const u32 hpd_ivb[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bdw[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
 };
 
 static const u32 hpd_ibx[HPD_NUM_PINS] = {
@@ -126,9 +126,9 @@ static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_bxt[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = BXT_DE_PORT_HP_DDI(HPD_PORT_A),
-	[HPD_PORT_B] = BXT_DE_PORT_HP_DDI(HPD_PORT_B),
-	[HPD_PORT_C] = BXT_DE_PORT_HP_DDI(HPD_PORT_C),
+	[HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
+	[HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
+	[HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
@@ -2364,7 +2364,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 					found = true;
 				}
 			} else if (IS_BROADWELL(dev_priv)) {
-				tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
+				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
 				if (tmp_mask) {
 					ilk_hpd_irq_handler(dev_priv, tmp_mask);
 					found = true;
@@ -3390,13 +3390,13 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	 * For BXT invert bit has to be set based on AOB design
 	 * for HPD detection logic, update it based on VBT fields.
 	 */
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_A)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
 		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_B)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
 		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & BXT_DE_PORT_HP_DDI(HPD_PORT_C)) &&
+	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
 	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
 		hotplug |= BXT_DDIC_HPD_INVERT;
 
@@ -3565,7 +3565,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
 	else if (IS_BROADWELL(dev_priv))
-		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
+		de_port_enables |= BDW_DE_PORT_HOTPLUG_MASK;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
 		enum transcoder trans;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ab570809d58..3584aee29a32 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7827,11 +7827,11 @@ enum {
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
-#define  BXT_DE_PORT_HP_DDI(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
-#define  BXT_DE_PORT_HOTPLUG_MASK	(BXT_DE_PORT_HP_DDI(HPD_PORT_A) | \
-					 BXT_DE_PORT_HP_DDI(HPD_PORT_B) | \
-					 BXT_DE_PORT_HP_DDI(HPD_PORT_C))
-#define  GEN8_PORT_DP_A_HOTPLUG		(1 << 3)
+#define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
+#define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
+					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
+#define  BDW_DE_PORT_HOTPLUG_MASK	GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
 #define  BXT_DE_PORT_GMBUS		(1 << 1)
 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
 #define  TGL_DE_PORT_AUX_USBC6		(1 << 13)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (7 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
                   ` (13 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin instead of port in the parametrized ICP+ DDI HPD
macros. Makes it clear what these refer to.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 12 ++++++------
 drivers/gpu/drm/i915/i915_reg.h | 34 ++++++++++++++++-----------------
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c84b6a0a17a2..d7dc2f5ed2b0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -141,9 +141,9 @@ static const u32 hpd_gen11[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
-	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
-	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
-	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
+	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
 	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
 	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
 	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
@@ -1066,11 +1066,11 @@ static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_A:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_A);
 	case HPD_PORT_B:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_B);
 	case HPD_PORT_C:
-		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(HPD_PORT_C);
 	default:
 		return false;
 	}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3584aee29a32..d7f027400c95 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,16 +8349,16 @@ enum {
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
-#define SDE_DDI_HOTPLUG_ICP(port)	(1 << ((port) + 16))
-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(PORT_C) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(PORT_A))
+#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
 #define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
 					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
@@ -8432,12 +8432,12 @@ enum {
  */
 
 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
-#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(port)		(0x8 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(port)	(0x3 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(port)		(0x0 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(port)	(0x1 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(port)	(0x2 << (4 * (port)))
-#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(port)	(0x3 << (4 * (port)))
+#define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
+#define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
 #define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
@@ -8447,15 +8447,15 @@ enum {
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
 #define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_1))
-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
+#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
 #define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
 					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (8 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:19   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
                   ` (12 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
to make it clear what they refer to.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++-----------------
 drivers/gpu/drm/i915/i915_reg.h | 37 ++++++++++++-------------
 2 files changed, 43 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d7dc2f5ed2b0..9c0b029cad07 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
 };
 
 static const u32 hpd_gen11[HPD_NUM_PINS] = {
-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
 };
 
 static const u32 hpd_icp[HPD_NUM_PINS] = {
@@ -1032,17 +1032,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -3256,21 +3256,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d7f027400c95..ae3c1710a438 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7813,6 +7813,7 @@ enum {
 	 GEN11_PIPE_PLANE5_FAULT)
 
 #define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
+#define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
 
 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
@@ -7890,27 +7891,27 @@ enum {
 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
-#define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
-						 GEN11_TC_HOTPLUG(TC_PORT_1))
-#define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
-						 GEN11_TBT_HOTPLUG(TC_PORT_1))
+#define  GEN11_TC_HOTPLUG(hpd_pin)		REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
+#define  GEN11_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
 
 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
-#define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
-#define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
+#define  GEN11_HOTPLUG_CTL_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin)		(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
 #define  GEN11_CSME			(31)
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
@ 2020-10-23 19:19   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:19 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:11PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Use hpd_pin instead of tc_port in the GEN11_{TC,TBT}_HOTPLUG()
>to make it clear what they refer to.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 48 ++++++++++++++++-----------------
> drivers/gpu/drm/i915/i915_reg.h | 37 ++++++++++++-------------
> 2 files changed, 43 insertions(+), 42 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index d7dc2f5ed2b0..9c0b029cad07 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -132,12 +132,12 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = {
> };
>
> static const u32 hpd_gen11[HPD_NUM_PINS] = {
>-	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(TC_PORT_1) | GEN11_TBT_HOTPLUG(TC_PORT_1),
>-	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(TC_PORT_2) | GEN11_TBT_HOTPLUG(TC_PORT_2),
>-	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(TC_PORT_3) | GEN11_TBT_HOTPLUG(TC_PORT_3),
>-	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(TC_PORT_4) | GEN11_TBT_HOTPLUG(TC_PORT_4),
>-	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(TC_PORT_5) | GEN11_TBT_HOTPLUG(TC_PORT_5),
>-	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(TC_PORT_6) | GEN11_TBT_HOTPLUG(TC_PORT_6),
>+	[HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
>+	[HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
>+	[HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
>+	[HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
>+	[HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
>+	[HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
> };
>
> static const u32 hpd_icp[HPD_NUM_PINS] = {
>@@ -1032,17 +1032,17 @@ static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> 	switch (pin) {
> 	case HPD_PORT_TC1:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_1);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC1);
> 	case HPD_PORT_TC2:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_2);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC2);
> 	case HPD_PORT_TC3:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_3);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC3);
> 	case HPD_PORT_TC4:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_4);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC4);
> 	case HPD_PORT_TC5:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_5);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC5);
> 	case HPD_PORT_TC6:
>-		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(TC_PORT_6);
>+		return val & GEN11_HOTPLUG_CTL_LONG_DETECT(HPD_PORT_TC6);
> 	default:
> 		return false;
> 	}
>@@ -3256,21 +3256,21 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 	u32 hotplug;
>
> 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
>+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
> 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
>
> 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
>-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_1) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_2) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_3) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_4) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_5) |
>-		   GEN11_HOTPLUG_CTL_ENABLE(TC_PORT_6);
>+	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
>+		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
> 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
> }
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index d7f027400c95..ae3c1710a438 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7813,6 +7813,7 @@ enum {
> 	 GEN11_PIPE_PLANE5_FAULT)
>
> #define _HPD_PIN_DDI(hpd_pin)	((hpd_pin) - HPD_PORT_A)
>+#define _HPD_PIN_TC(hpd_pin)	((hpd_pin) - HPD_PORT_TC1)
>
> #define GEN8_DE_PORT_ISR _MMIO(0x44440)
> #define GEN8_DE_PORT_IMR _MMIO(0x44444)
>@@ -7890,27 +7891,27 @@ enum {
> #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
> #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
> #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
>-#define  GEN11_TC_HOTPLUG(tc_port)		(1 << ((tc_port) + 16))
>-#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(TC_PORT_6) | \
>-						 GEN11_TC_HOTPLUG(TC_PORT_5) | \
>-						 GEN11_TC_HOTPLUG(TC_PORT_4) | \
>-						 GEN11_TC_HOTPLUG(TC_PORT_3) | \
>-						 GEN11_TC_HOTPLUG(TC_PORT_2) | \
>-						 GEN11_TC_HOTPLUG(TC_PORT_1))
>-#define  GEN11_TBT_HOTPLUG(tc_port)		(1 << (tc_port))
>-#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(TC_PORT_6) | \
>-						 GEN11_TBT_HOTPLUG(TC_PORT_5) | \
>-						 GEN11_TBT_HOTPLUG(TC_PORT_4) | \
>-						 GEN11_TBT_HOTPLUG(TC_PORT_3) | \
>-						 GEN11_TBT_HOTPLUG(TC_PORT_2) | \
>-						 GEN11_TBT_HOTPLUG(TC_PORT_1))
>+#define  GEN11_TC_HOTPLUG(hpd_pin)		REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
>+#define  GEN11_DE_TC_HOTPLUG_MASK		(GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
>+						 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
>+						 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
>+						 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
>+						 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
>+						 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
>+#define  GEN11_TBT_HOTPLUG(hpd_pin)		REG_BIT(_HPD_PIN_TC(hpd_pin))
>+#define  GEN11_DE_TBT_HOTPLUG_MASK		(GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
>+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
>+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
>+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
>+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
>+						 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
>
> #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
> #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
>-#define  GEN11_HOTPLUG_CTL_ENABLE(tc_port)		(8 << (tc_port) * 4)
>-#define  GEN11_HOTPLUG_CTL_LONG_DETECT(tc_port)		(2 << (tc_port) * 4)
>-#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>-#define  GEN11_HOTPLUG_CTL_NO_DETECT(tc_port)		(0 << (tc_port) * 4)
>+#define  GEN11_HOTPLUG_CTL_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
>+#define  GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin)		(2 << (_HPD_PIN_TC(hpd_pin) * 4))
>+#define  GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
>+#define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
>
> #define GEN11_GT_INTR_DW0		_MMIO(0x190018)
> #define  GEN11_CSME			(31)
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (9 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:20   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
                   ` (11 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Parametrize the icp+ TC HPD bits using hpd_pin rather than
tc_port so it's clear what kind of an animal we're dealing
with.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++-------------
 drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++-----------------
 2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9c0b029cad07..ff695ff23ce5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
 };
 
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -1080,17 +1080,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
 	case HPD_PORT_TC1:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
 	case HPD_PORT_TC2:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
 	case HPD_PORT_TC3:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
 	case HPD_PORT_TC4:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
 	case HPD_PORT_TC5:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
 	case HPD_PORT_TC6:
-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
 	default:
 		return false;
 	}
@@ -1869,7 +1869,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		tc_hotplug_trigger = 0;
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
 	} else {
 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
 			 "Unrecognized PCH type 0x%x\n",
@@ -3237,7 +3237,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
 }
 
 /*
@@ -3643,7 +3643,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
 	} else {
 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae3c1710a438..8f26ab69b366 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8349,23 +8349,23 @@ enum {
 
 /* south display engine interrupt: ICP/TGP */
 #define SDE_GMBUS_ICP			(1 << 23)
-#define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
+#define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
 #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8441,24 +8441,24 @@ enum {
 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
 
 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
-#define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
-#define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
-#define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
+#define   ICP_TC_HPD_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_LONG_DETECT(hpd_pin)	(2 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define   ICP_TC_HPD_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
 
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
 #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_1))
+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
 #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
-					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
 
 #define _PCH_DPLL_A              0xc6014
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
@ 2020-10-23 19:20   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:20 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:12PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Parametrize the icp+ TC HPD bits using hpd_pin rather than
>tc_port so it's clear what kind of an animal we're dealing
>with.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++-------------
> drivers/gpu/drm/i915/i915_reg.h | 40 ++++++++++++++++-----------------
> 2 files changed, 35 insertions(+), 35 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 9c0b029cad07..ff695ff23ce5 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -144,12 +144,12 @@ static const u32 hpd_icp[HPD_NUM_PINS] = {
> 	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
> 	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
> 	[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
>-	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(TC_PORT_1),
>-	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(TC_PORT_2),
>-	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(TC_PORT_3),
>-	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(TC_PORT_4),
>-	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(TC_PORT_5),
>-	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(TC_PORT_6),
>+	[HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
>+	[HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
>+	[HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
>+	[HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
>+	[HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
>+	[HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
> };
>
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
>@@ -1080,17 +1080,17 @@ static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
> {
> 	switch (pin) {
> 	case HPD_PORT_TC1:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_1);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC1);
> 	case HPD_PORT_TC2:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_2);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC2);
> 	case HPD_PORT_TC3:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_3);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC3);
> 	case HPD_PORT_TC4:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_4);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC4);
> 	case HPD_PORT_TC5:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_5);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC5);
> 	case HPD_PORT_TC6:
>-		return val & ICP_TC_HPD_LONG_DETECT(TC_PORT_6);
>+		return val & ICP_TC_HPD_LONG_DETECT(HPD_PORT_TC6);
> 	default:
> 		return false;
> 	}
>@@ -1869,7 +1869,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> 		tc_hotplug_trigger = 0;
> 	} else if (HAS_PCH_MCC(dev_priv)) {
> 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(TC_PORT_1);
>+		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
> 	} else {
> 		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
> 			 "Unrecognized PCH type 0x%x\n",
>@@ -3237,7 +3237,7 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
> static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> 	icp_hpd_irq_setup(dev_priv,
>-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(TC_PORT_1));
>+			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
> }
>
> /*
>@@ -3643,7 +3643,7 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> 		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
> 	} else if (HAS_PCH_MCC(dev_priv)) {
> 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
>-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(TC_PORT_1));
>+		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
> 	} else {
> 		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
> 		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index ae3c1710a438..8f26ab69b366 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8349,23 +8349,23 @@ enum {
>
> /* south display engine interrupt: ICP/TGP */
> #define SDE_GMBUS_ICP			(1 << 23)
>-#define SDE_TC_HOTPLUG_ICP(tc_port)	(1 << ((tc_port) + 24))
>+#define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
> #define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
>+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> #define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(TC_PORT_6) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_5) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_4) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_3) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_2) | \
>-					 SDE_TC_HOTPLUG_ICP(TC_PORT_1))
>+#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>+					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>
> #define SDEISR  _MMIO(0xc4000)
> #define SDEIMR  _MMIO(0xc4004)
>@@ -8441,24 +8441,24 @@ enum {
> #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
>
> #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
>-#define   ICP_TC_HPD_ENABLE(tc_port)		(8 << (tc_port) * 4)
>-#define   ICP_TC_HPD_LONG_DETECT(tc_port)	(2 << (tc_port) * 4)
>-#define   ICP_TC_HPD_SHORT_DETECT(tc_port)	(1 << (tc_port) * 4)
>+#define   ICP_TC_HPD_ENABLE(hpd_pin)		(8 << (_HPD_PIN_TC(hpd_pin) * 4))
>+#define   ICP_TC_HPD_LONG_DETECT(hpd_pin)	(2 << (_HPD_PIN_TC(hpd_pin) * 4))
>+#define   ICP_TC_HPD_SHORT_DETECT(hpd_pin)	(1 << (_HPD_PIN_TC(hpd_pin) * 4))
>
> #define SHPD_FILTER_CNT				_MMIO(0xc4038)
> #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
>
> #define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
>-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_4) | \
>-					 ICP_TC_HPD_ENABLE(TC_PORT_3) | \
>-					 ICP_TC_HPD_ENABLE(TC_PORT_2) | \
>-					 ICP_TC_HPD_ENABLE(TC_PORT_1))
>+#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
>+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
>+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
>+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
> #define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
> 					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
>-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(TC_PORT_6) | \
>-					 ICP_TC_HPD_ENABLE(TC_PORT_5) | \
>+#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
>+					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
> 					 ICP_TC_HPD_ENABLE_MASK)
>
> #define _PCH_DPLL_A              0xc6014
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (10 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:21   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
                   ` (10 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
the file so we can use them in more places. No functional changes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index ff695ff23ce5..68e9d2813d32 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1193,6 +1193,31 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
 
 }
 
+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 enabled_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+			enabled_irqs |= hpd[encoder->hpd_pin];
+
+	return enabled_irqs;
+}
+
+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
+				  const u32 hpd[HPD_NUM_PINS])
+{
+	struct intel_encoder *encoder;
+	u32 hotplug_irqs = 0;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder)
+		hotplug_irqs |= hpd[encoder->hpd_pin];
+
+	return hotplug_irqs;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
 	wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3130,31 +3155,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
-{
-	struct intel_encoder *encoder;
-	u32 enabled_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
-			enabled_irqs |= hpd[encoder->hpd_pin];
-
-	return enabled_irqs;
-}
-
-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
-				  const u32 hpd[HPD_NUM_PINS])
-{
-	struct intel_encoder *encoder;
-	u32 hotplug_irqs = 0;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder)
-		hotplug_irqs |= hpd[encoder->hpd_pin];
-
-	return hotplug_irqs;
-}
-
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
@ 2020-10-23 19:21   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:21 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:13PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Move intel_hpd_{enabled,hotplug}_irqs() closes to the beginning of
>the file so we can use them in more places. No functional changes.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/i915_irq.c | 50 ++++++++++++++++-----------------
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index ff695ff23ce5..68e9d2813d32 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -1193,6 +1193,31 @@ static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
>
> }
>
>+static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
>+				  const u32 hpd[HPD_NUM_PINS])
>+{
>+	struct intel_encoder *encoder;
>+	u32 enabled_irqs = 0;
>+
>+	for_each_intel_encoder(&dev_priv->drm, encoder)
>+		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
>+			enabled_irqs |= hpd[encoder->hpd_pin];
>+
>+	return enabled_irqs;
>+}
>+
>+static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
>+				  const u32 hpd[HPD_NUM_PINS])
>+{
>+	struct intel_encoder *encoder;
>+	u32 hotplug_irqs = 0;
>+
>+	for_each_intel_encoder(&dev_priv->drm, encoder)
>+		hotplug_irqs |= hpd[encoder->hpd_pin];
>+
>+	return hotplug_irqs;
>+}
>+
> static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
> {
> 	wake_up_all(&dev_priv->gmbus_wait_queue);
>@@ -3130,31 +3155,6 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
> 	spin_unlock_irq(&dev_priv->irq_lock);
> }
>
>-static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
>-				  const u32 hpd[HPD_NUM_PINS])
>-{
>-	struct intel_encoder *encoder;
>-	u32 enabled_irqs = 0;
>-
>-	for_each_intel_encoder(&dev_priv->drm, encoder)
>-		if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
>-			enabled_irqs |= hpd[encoder->hpd_pin];
>-
>-	return enabled_irqs;
>-}
>-
>-static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
>-				  const u32 hpd[HPD_NUM_PINS])
>-{
>-	struct intel_encoder *encoder;
>-	u32 hotplug_irqs = 0;
>-
>-	for_each_intel_encoder(&dev_priv->drm, encoder)
>-		hotplug_irqs |= hpd[encoder->hpd_pin];
>-
>-	return hotplug_irqs;
>-}
>-
> static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (11 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:23   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
                   ` (9 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason to stuff both type-c and tbt into the same function.
Let's split this so we may more easily handle platforms that
lack the tbt spefific bits.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 68e9d2813d32..2c8813f34a45 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3251,7 +3251,7 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 			  TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
@@ -3263,6 +3263,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
+}
+
+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
+{
+	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
 	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
@@ -3288,7 +3293,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_DE_HPD_IMR, val);
 	POSTING_READ(GEN11_DE_HPD_IMR);
 
-	gen11_hpd_detection_setup(dev_priv);
+	gen11_tc_hpd_detection_setup(dev_priv);
+	gen11_tbt_hpd_detection_setup(dev_priv);
 
 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
 		icp_hpd_irq_setup(dev_priv,
@@ -3603,7 +3609,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
 			      de_hpd_enables);
-		gen11_hpd_detection_setup(dev_priv);
+		gen11_tc_hpd_detection_setup(dev_priv);
+		gen11_tbt_hpd_detection_setup(dev_priv);
 	} else if (IS_GEN9_LP(dev_priv)) {
 		bxt_hpd_detection_setup(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
@ 2020-10-23 19:23   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:23 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:14PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>No reason to stuff both type-c and tbt into the same function.
>Let's split this so we may more easily handle platforms that
>lack the tbt spefific bits.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_irq.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 68e9d2813d32..2c8813f34a45 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -3251,7 +3251,7 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 			  TGP_DDI_HPD_ENABLE_MASK, 0);
> }
>
>-static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
>+static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
> {
> 	u32 hotplug;
>
>@@ -3263,6 +3263,11 @@ static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
> 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
> 		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
> 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
>+}
>+
>+static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
>+{
>+	u32 hotplug;
>
> 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
> 	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
>@@ -3288,7 +3293,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> 	I915_WRITE(GEN11_DE_HPD_IMR, val);
> 	POSTING_READ(GEN11_DE_HPD_IMR);
>
>-	gen11_hpd_detection_setup(dev_priv);
>+	gen11_tc_hpd_detection_setup(dev_priv);
>+	gen11_tbt_hpd_detection_setup(dev_priv);
>
> 	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
> 		icp_hpd_irq_setup(dev_priv,
>@@ -3603,7 +3609,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>
> 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
> 			      de_hpd_enables);
>-		gen11_hpd_detection_setup(dev_priv);
>+		gen11_tc_hpd_detection_setup(dev_priv);
>+		gen11_tbt_hpd_detection_setup(dev_priv);
> 	} else if (IS_GEN9_LP(dev_priv)) {
> 		bxt_hpd_detection_setup(dev_priv);
> 	} else if (IS_BROADWELL(dev_priv)) {
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall()
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (12 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask' Ville Syrjala
                   ` (8 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason that I can see why we should enable the hpd detection logic
already during irq postinstall phase. We don't even do this on all
the platforms. We just need it before we actually enable the hotplug
interrupts in .hpd_irq_setup(), and in fact we already do it there as
well. Let's just eliminate the redundant early setup.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 38 +++------------------------------
 1 file changed, 3 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2c8813f34a45..b1f21502b78b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3377,8 +3377,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_irq_setup(dev_priv);
 }
 
-static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				      u32 enabled_irqs)
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
+				    u32 enabled_irqs)
 {
 	u32 hotplug;
 
@@ -3409,11 +3409,6 @@ static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
-{
-	__bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
-}
-
 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
@@ -3423,7 +3418,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-	__bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
 }
 
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3442,12 +3437,6 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
-	    HAS_PCH_LPT(dev_priv))
-		ibx_hpd_detection_setup(dev_priv);
-	else
-		spt_hpd_detection_setup(dev_priv);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3487,8 +3476,6 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
 		      display_mask | extra_mask);
 
-	ilk_hpd_detection_setup(dev_priv);
-
 	ibx_irq_postinstall(dev_priv);
 }
 
@@ -3609,12 +3596,6 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 		GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
 			      de_hpd_enables);
-		gen11_tc_hpd_detection_setup(dev_priv);
-		gen11_tbt_hpd_detection_setup(dev_priv);
-	} else if (IS_GEN9_LP(dev_priv)) {
-		bxt_hpd_detection_setup(dev_priv);
-	} else if (IS_BROADWELL(dev_priv)) {
-		ilk_hpd_detection_setup(dev_priv);
 	}
 }
 
@@ -3642,19 +3623,6 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
-
-	if (HAS_PCH_TGP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, TGP_TC_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK);
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-	} else {
-		icp_ddi_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK);
-		icp_tc_hpd_detection_setup(dev_priv, ICP_TC_HPD_ENABLE_MASK);
-	}
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask'
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (13 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:25   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
                   ` (7 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace this silly tmp_mask with hotplug_trigger/te_trigger
where appropriate.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1f21502b78b..be69c129dd5a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2371,7 +2371,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	if (master_ctl & GEN8_DE_PORT_IRQ) {
 		iir = I915_READ(GEN8_DE_PORT_IIR);
 		if (iir) {
-			u32 tmp_mask;
 			bool found = false;
 
 			I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2383,15 +2382,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			}
 
 			if (IS_GEN9_LP(dev_priv)) {
-				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
-				if (tmp_mask) {
-					bxt_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			} else if (IS_BROADWELL(dev_priv)) {
-				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
-				if (tmp_mask) {
-					ilk_hpd_irq_handler(dev_priv, tmp_mask);
+				u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
+
+				if (hotplug_trigger) {
+					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
 					found = true;
 				}
 			}
@@ -2402,9 +2403,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			}
 
 			if (INTEL_GEN(dev_priv) >= 11) {
-				tmp_mask = iir & (DSI0_TE | DSI1_TE);
-				if (tmp_mask) {
-					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
+				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
+
+				if (te_trigger) {
+					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
 					found = true;
 				}
 			}
-- 
2.26.2

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask'
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask' Ville Syrjala
@ 2020-10-23 19:25   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:25 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:16PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Replace this silly tmp_mask with hotplug_trigger/te_trigger
>where appropriate.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_irq.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b1f21502b78b..be69c129dd5a 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -2371,7 +2371,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> 	if (master_ctl & GEN8_DE_PORT_IRQ) {
> 		iir = I915_READ(GEN8_DE_PORT_IIR);
> 		if (iir) {
>-			u32 tmp_mask;
> 			bool found = false;
>
> 			I915_WRITE(GEN8_DE_PORT_IIR, iir);
>@@ -2383,15 +2382,17 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> 			}
>
> 			if (IS_GEN9_LP(dev_priv)) {
>-				tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
>-				if (tmp_mask) {
>-					bxt_hpd_irq_handler(dev_priv, tmp_mask);
>+				u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
>+
>+				if (hotplug_trigger) {
>+					bxt_hpd_irq_handler(dev_priv, hotplug_trigger);
> 					found = true;
> 				}
> 			} else if (IS_BROADWELL(dev_priv)) {
>-				tmp_mask = iir & BDW_DE_PORT_HOTPLUG_MASK;
>-				if (tmp_mask) {
>-					ilk_hpd_irq_handler(dev_priv, tmp_mask);
>+				u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;
>+
>+				if (hotplug_trigger) {
>+					ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
> 					found = true;
> 				}
> 			}
>@@ -2402,9 +2403,10 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> 			}
>
> 			if (INTEL_GEN(dev_priv) >= 11) {
>-				tmp_mask = iir & (DSI0_TE | DSI1_TE);
>-				if (tmp_mask) {
>-					gen11_dsi_te_interrupt_handler(dev_priv, tmp_mask);
>+				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
>+
>+				if (te_trigger) {
>+					gen11_dsi_te_interrupt_handler(dev_priv, te_trigger);
> 					found = true;
> 				}
> 			}
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (14 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask' Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:29   ` Lucas De Marchi
  2020-10-23 19:30   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 17/19] drm/i915: Enable hpd logic only for ports that are present Ville Syrjala
                   ` (6 subsequent siblings)
  22 siblings, 2 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We no longer unmask all HPD irqs, so we can drop the ugly per-platform
HPD IIR masking. IMR will prevent unsupported bits from appearing in
IIR.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
 drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
 2 files changed, 4 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index be69c129dd5a..447a52f7701d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1883,27 +1883,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 
 static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 {
-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
 	u32 pin_mask = 0, long_mask = 0;
 
-	if (HAS_PCH_TGP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
-	} else if (HAS_PCH_JSP(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
-		tc_hotplug_trigger = 0;
-	} else if (HAS_PCH_MCC(dev_priv)) {
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
-	} else {
-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
-			 "Unrecognized PCH type 0x%x\n",
-			 INTEL_PCH_TYPE(dev_priv));
-
-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
-	}
-
 	if (ddi_hotplug_trigger) {
 		u32 dig_hotplug_reg;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f26ab69b366..f15914fbe7c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8351,16 +8351,10 @@ enum {
 #define SDE_GMBUS_ICP			(1 << 23)
 #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
 #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
-- 
2.26.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
@ 2020-10-23 19:29   ` Lucas De Marchi
  2020-10-23 19:44     ` Ville Syrjälä
  2020-10-23 19:30   ` Lucas De Marchi
  1 sibling, 1 reply; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:29 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:17PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>We no longer unmask all HPD irqs, so we can drop the ugly per-platform
>HPD IIR masking. IMR will prevent unsupported bits from appearing in
>IIR.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

this patch should come after
"drm/i915: Enable hpd logic only for ports that are present"

>---
> drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
> drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
> 2 files changed, 4 insertions(+), 27 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index be69c129dd5a..447a52f7701d 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -1883,27 +1883,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
>-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> 	u32 pin_mask = 0, long_mask = 0;
>
>-	if (HAS_PCH_TGP(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>-	} else if (HAS_PCH_JSP(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>-		tc_hotplug_trigger = 0;
>-	} else if (HAS_PCH_MCC(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
>-	} else {
>-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
>-			 "Unrecognized PCH type 0x%x\n",
>-			 INTEL_PCH_TYPE(dev_priv));
>-
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>-	}
>-
> 	if (ddi_hotplug_trigger) {
> 		u32 dig_hotplug_reg;
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 8f26ab69b366..f15914fbe7c3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8351,16 +8351,10 @@ enum {
> #define SDE_GMBUS_ICP			(1 << 23)
> #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
>+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))

and here is the opportunity to rename this to SDE_DDI_HOTPLUG_MASK_ICP
or in a separate patch.

with the patch reorder,


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
>+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking
  2020-10-23 19:29   ` Lucas De Marchi
@ 2020-10-23 19:44     ` Ville Syrjälä
  2020-10-28  1:00       ` Lucas De Marchi
  0 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjälä @ 2020-10-23 19:44 UTC (permalink / raw)
  To: Lucas De Marchi; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 12:29:37PM -0700, Lucas De Marchi wrote:
> On Fri, Oct 23, 2020 at 04:34:17PM +0300, Ville Syrjälä wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >We no longer unmask all HPD irqs, so we can drop the ugly per-platform
> >HPD IIR masking. IMR will prevent unsupported bits from appearing in
> >IIR.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> this patch should come after
> "drm/i915: Enable hpd logic only for ports that are present"

The order should not matter. We already mask out all unwanted bits
from IIR via IMR, so whether or not the HPD level is visible in ISR
for some unused pin is irrelevant.

> 
> >---
> > drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
> > drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
> > 2 files changed, 4 insertions(+), 27 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> >index be69c129dd5a..447a52f7701d 100644
> >--- a/drivers/gpu/drm/i915/i915_irq.c
> >+++ b/drivers/gpu/drm/i915/i915_irq.c
> >@@ -1883,27 +1883,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> >
> > static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> > {
> >-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
> >+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> >+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> > 	u32 pin_mask = 0, long_mask = 0;
> >
> >-	if (HAS_PCH_TGP(dev_priv)) {
> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> >-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
> >-	} else if (HAS_PCH_JSP(dev_priv)) {
> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
> >-		tc_hotplug_trigger = 0;
> >-	} else if (HAS_PCH_MCC(dev_priv)) {
> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> >-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
> >-	} else {
> >-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
> >-			 "Unrecognized PCH type 0x%x\n",
> >-			 INTEL_PCH_TYPE(dev_priv));
> >-
> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
> >-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> >-	}
> >-
> > 	if (ddi_hotplug_trigger) {
> > 		u32 dig_hotplug_reg;
> >
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >index 8f26ab69b366..f15914fbe7c3 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -8351,16 +8351,10 @@ enum {
> > #define SDE_GMBUS_ICP			(1 << 23)
> > #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> > #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
> >-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> >-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
> >-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> >-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> >+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> > 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> > 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
> 
> and here is the opportunity to rename this to SDE_DDI_HOTPLUG_MASK_ICP
> or in a separate patch.
> 
> with the patch reorder,
> 
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> Lucas De Marchi
> 
> >-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> >+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
> >-- 
> >2.26.2
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking
  2020-10-23 19:44     ` Ville Syrjälä
@ 2020-10-28  1:00       ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-28  1:00 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 10:44:29PM +0300, Ville Syrjälä wrote:
>On Fri, Oct 23, 2020 at 12:29:37PM -0700, Lucas De Marchi wrote:
>> On Fri, Oct 23, 2020 at 04:34:17PM +0300, Ville Syrjälä wrote:
>> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> >We no longer unmask all HPD irqs, so we can drop the ugly per-platform
>> >HPD IIR masking. IMR will prevent unsupported bits from appearing in
>> >IIR.
>> >
>> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> this patch should come after
>> "drm/i915: Enable hpd logic only for ports that are present"
>
>The order should not matter. We already mask out all unwanted bits
>from IIR via IMR, so whether or not the HPD level is visible in ISR
>for some unused pin is irrelevant.

indeed. My R-B stands even more now.

Lucas De Marchi

>
>>
>> >---
>> > drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
>> > drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
>> > 2 files changed, 4 insertions(+), 27 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> >index be69c129dd5a..447a52f7701d 100644
>> >--- a/drivers/gpu/drm/i915/i915_irq.c
>> >+++ b/drivers/gpu/drm/i915/i915_irq.c
>> >@@ -1883,27 +1883,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> >
>> > static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>> > {
>> >-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>> >+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> >+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> > 	u32 pin_mask = 0, long_mask = 0;
>> >
>> >-	if (HAS_PCH_TGP(dev_priv)) {
>> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> >-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>> >-	} else if (HAS_PCH_JSP(dev_priv)) {
>> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>> >-		tc_hotplug_trigger = 0;
>> >-	} else if (HAS_PCH_MCC(dev_priv)) {
>> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> >-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
>> >-	} else {
>> >-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
>> >-			 "Unrecognized PCH type 0x%x\n",
>> >-			 INTEL_PCH_TYPE(dev_priv));
>> >-
>> >-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>> >-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>> >-	}
>> >-
>> > 	if (ddi_hotplug_trigger) {
>> > 		u32 dig_hotplug_reg;
>> >
>> >diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> >index 8f26ab69b366..f15914fbe7c3 100644
>> >--- a/drivers/gpu/drm/i915/i915_reg.h
>> >+++ b/drivers/gpu/drm/i915/i915_reg.h
>> >@@ -8351,16 +8351,10 @@ enum {
>> > #define SDE_GMBUS_ICP			(1 << 23)
>> > #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
>> > #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>> >-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>> >-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>> >-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>> >-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>> >-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
>> >+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
>> > 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>> > 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>>
>> and here is the opportunity to rename this to SDE_DDI_HOTPLUG_MASK_ICP
>> or in a separate patch.
>>
>> with the patch reorder,
>>
>>
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>> Lucas De Marchi
>>
>> >-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
>> >+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
>> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
>> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>> > 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>> >--
>> >2.26.2
>> >
>> >_______________________________________________
>> >Intel-gfx mailing list
>> >Intel-gfx@lists.freedesktop.org
>> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>-- 
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
  2020-10-23 19:29   ` Lucas De Marchi
@ 2020-10-23 19:30   ` Lucas De Marchi
  1 sibling, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:30 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

While changing this, may fix the typo on subject: "per-platform"

Lucas De Marchi

On Fri, Oct 23, 2020 at 04:34:17PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>We no longer unmask all HPD irqs, so we can drop the ugly per-platform
>HPD IIR masking. IMR will prevent unsupported bits from appearing in
>IIR.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/i915_irq.c | 21 ++-------------------
> drivers/gpu/drm/i915/i915_reg.h | 10 ++--------
> 2 files changed, 4 insertions(+), 27 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index be69c129dd5a..447a52f7701d 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -1883,27 +1883,10 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
>-	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
>+	u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>+	u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
> 	u32 pin_mask = 0, long_mask = 0;
>
>-	if (HAS_PCH_TGP(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
>-	} else if (HAS_PCH_JSP(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
>-		tc_hotplug_trigger = 0;
>-	} else if (HAS_PCH_MCC(dev_priv)) {
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1);
>-	} else {
>-		drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
>-			 "Unrecognized PCH type 0x%x\n",
>-			 INTEL_PCH_TYPE(dev_priv));
>-
>-		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
>-		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
>-	}
>-
> 	if (ddi_hotplug_trigger) {
> 		u32 dig_hotplug_reg;
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 8f26ab69b366..f15914fbe7c3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -8351,16 +8351,10 @@ enum {
> #define SDE_GMBUS_ICP			(1 << 23)
> #define SDE_TC_HOTPLUG_ICP(hpd_pin)	REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
> #define SDE_DDI_HOTPLUG_ICP(hpd_pin)	REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
>-#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
>-					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>-#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>-					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>-#define SDE_DDI_MASK_TGP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
>+#define SDE_DDI_MASK_ICP		(SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
> 					 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
>-#define SDE_TC_MASK_TGP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
>+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
> 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
>-- 
>2.26.2
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 17/19] drm/i915: Enable hpd logic only for ports that are present
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (15 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
                   ` (5 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's enable the hardware hpd logic only for the ports we
can actually use.

In theory this may save some miniscule amounts of power,
and more importantly it eliminates a lot if platform specific
codepaths since the generic thing can now deal with any
combination of ports being present on each SKU.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 301 ++++++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h |  13 --
 2 files changed, 205 insertions(+), 109 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 447a52f7701d..04a6f322110d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -61,6 +61,8 @@
  */
 
 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
+typedef u32 (*hotplug_enables_func)(struct drm_i915_private *i915,
+				    enum hpd_pin pin);
 
 static const u32 hpd_ilk[HPD_NUM_PINS] = {
 	[HPD_PORT_A] = DE_DP_A_HOTPLUG,
@@ -1218,6 +1220,18 @@ static u32 intel_hpd_hotplug_irqs(struct drm_i915_private *dev_priv,
 	return hotplug_irqs;
 }
 
+static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
+				     hotplug_enables_func hotplug_enables)
+{
+	struct intel_encoder *encoder;
+	u32 hotplug = 0;
+
+	for_each_intel_encoder(&i915->drm, encoder)
+		hotplug |= hotplug_enables(i915, encoder->hpd_pin);
+
+	return hotplug;
+}
+
 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
 {
 	wake_up_all(&dev_priv->gmbus_wait_queue);
@@ -3140,6 +3154,31 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+static u32 ibx_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		/*
+		 * When CPU and PCH are on the same package, port A
+		 * HPD must be enabled in both north and south.
+		 */
+		return HAS_PCH_LPT_LP(i915) ?
+			PORTA_HOTPLUG_ENABLE : 0;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE |
+			PORTB_PULSE_DURATION_2ms;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE |
+			PORTC_PULSE_DURATION_2ms;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE |
+			PORTD_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
+}
+
 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3150,18 +3189,14 @@ static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on LPT+.
 	 */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug &= ~(PORTB_PULSE_DURATION_MASK |
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE |
+		     PORTB_PULSE_DURATION_MASK |
 		     PORTC_PULSE_DURATION_MASK |
 		     PORTD_PULSE_DURATION_MASK);
-	hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
-	hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
-	hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
-	/*
-	 * When CPU and PCH are on the same package, port A
-	 * HPD must be enabled in both north and south.
-	 */
-	if (HAS_PCH_LPT_LP(dev_priv))
-		hotplug |= PORTA_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ibx_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3177,28 +3212,63 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_detection_setup(dev_priv);
 }
 
-static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv,
-					u32 enable_mask)
+static u32 icp_ddi_hotplug_enables(struct drm_i915_private *i915,
+				   enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+	case HPD_PORT_B:
+	case HPD_PORT_C:
+		return SHOTPLUG_CTL_DDI_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static u32 icp_tc_hotplug_enables(struct drm_i915_private *i915,
+				  enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return ICP_TC_HPD_ENABLE(pin);
+	default:
+		return 0;
+	}
+}
+
+static void icp_ddi_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_DDI);
-	hotplug |= enable_mask;
+	hotplug &= ~(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) |
+		     SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_ddi_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
 }
 
-static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				       u32 enable_mask)
+static void icp_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(SHOTPLUG_CTL_TC);
-	hotplug |= enable_mask;
+	hotplug &= ~(ICP_TC_HPD_ENABLE(HPD_PORT_TC1) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC2) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC3) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC4) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC5) |
+		     ICP_TC_HPD_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, icp_tc_hotplug_enables);
 	I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
 }
 
-static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
-			      u32 ddi_enable_mask, u32 tc_enable_mask)
+static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug_irqs, enabled_irqs;
 
@@ -3210,30 +3280,24 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
 
 	ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
 
-	icp_ddi_hpd_detection_setup(dev_priv, ddi_enable_mask);
-	if (tc_enable_mask)
-		icp_tc_hpd_detection_setup(dev_priv, tc_enable_mask);
+	icp_ddi_hpd_detection_setup(dev_priv);
+	icp_tc_hpd_detection_setup(dev_priv);
 }
 
-/*
- * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
- * equivalent of SDE.
- */
-static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
+static u32 gen11_hotplug_enables(struct drm_i915_private *i915,
+				 enum hpd_pin pin)
 {
-	icp_hpd_irq_setup(dev_priv,
-			  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(HPD_PORT_TC1));
-}
-
-/*
- * JSP behaves exactly the same as MCC above except that port C is mapped to
- * the DDI-C pins instead of the TC1 pins.  This means we should follow TGP's
- * masks & tables rather than ICP's masks & tables.
- */
-static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
-{
-	icp_hpd_irq_setup(dev_priv,
-			  TGP_DDI_HPD_ENABLE_MASK, 0);
+	switch (pin) {
+	case HPD_PORT_TC1:
+	case HPD_PORT_TC2:
+	case HPD_PORT_TC3:
+	case HPD_PORT_TC4:
+	case HPD_PORT_TC5:
+	case HPD_PORT_TC6:
+		return GEN11_HOTPLUG_CTL_ENABLE(pin);
+	default:
+		return 0;
+	}
 }
 
 static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3241,12 +3305,13 @@ static void gen11_tc_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
 }
 
@@ -3255,12 +3320,13 @@ static void gen11_tbt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	u32 hotplug;
 
 	hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
-	hotplug |= GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
-		   GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6);
+	hotplug &= ~(GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC1) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC2) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC3) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC4) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC5) |
+		     GEN11_HOTPLUG_CTL_ENABLE(HPD_PORT_TC6));
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, gen11_hotplug_enables);
 	I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
 }
 
@@ -3281,12 +3347,36 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	gen11_tc_hpd_detection_setup(dev_priv);
 	gen11_tbt_hpd_detection_setup(dev_priv);
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
-		icp_hpd_irq_setup(dev_priv,
-				  TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
-	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-		icp_hpd_irq_setup(dev_priv,
-				  ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+		icp_hpd_irq_setup(dev_priv);
+}
+
+static u32 spt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return PORTA_HOTPLUG_ENABLE;
+	case HPD_PORT_B:
+		return PORTB_HOTPLUG_ENABLE;
+	case HPD_PORT_C:
+		return PORTC_HOTPLUG_ENABLE;
+	case HPD_PORT_D:
+		return PORTD_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
+}
+
+static u32 spt_hotplug2_enables(struct drm_i915_private *i915,
+				enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_E:
+		return PORTE_HOTPLUG_ENABLE;
+	default:
+		return 0;
+	}
 }
 
 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
@@ -3303,14 +3393,16 @@ static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 
 	/* Enable digital hotplug on the PCH */
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE |
-		   PORTD_HOTPLUG_ENABLE;
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     PORTD_HOTPLUG_ENABLE);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 
 	hotplug = I915_READ(PCH_PORT_HOTPLUG2);
-	hotplug |= PORTE_HOTPLUG_ENABLE;
+	hotplug &= ~PORTE_HOTPLUG_ENABLE;
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, spt_hotplug2_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
 }
 
@@ -3329,6 +3421,18 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	spt_hpd_detection_setup(dev_priv);
 }
 
+static u32 ilk_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return DIGITAL_PORTA_HOTPLUG_ENABLE |
+			DIGITAL_PORTA_PULSE_DURATION_2ms;
+	default:
+		return 0;
+	}
+}
+
 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3339,9 +3443,9 @@ static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
 	 * The pulse duration bits are reserved on HSW+.
 	 */
 	hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
-	hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
-	hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
-		   DIGITAL_PORTA_PULSE_DURATION_2ms;
+	hotplug &= ~(DIGITAL_PORTA_HOTPLUG_ENABLE |
+		     DIGITAL_PORTA_PULSE_DURATION_MASK);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, ilk_hotplug_enables);
 	I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
 }
 
@@ -3362,35 +3466,44 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	ibx_hpd_irq_setup(dev_priv);
 }
 
-static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
-				    u32 enabled_irqs)
+static u32 bxt_hotplug_enables(struct drm_i915_private *i915,
+			       enum hpd_pin pin)
+{
+	u32 hotplug;
+
+	switch (pin) {
+	case HPD_PORT_A:
+		hotplug = PORTA_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_A))
+			hotplug |= BXT_DDIA_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_B:
+		hotplug = PORTB_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_B))
+			hotplug |= BXT_DDIB_HPD_INVERT;
+		return hotplug;
+	case HPD_PORT_C:
+		hotplug = PORTC_HOTPLUG_ENABLE;
+		if (intel_bios_is_port_hpd_inverted(i915, PORT_C))
+			hotplug |= BXT_DDIC_HPD_INVERT;
+		return hotplug;
+	default:
+		return 0;
+	}
+}
+
+static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
 
 	hotplug = I915_READ(PCH_PORT_HOTPLUG);
-	hotplug |= PORTA_HOTPLUG_ENABLE |
-		   PORTB_HOTPLUG_ENABLE |
-		   PORTC_HOTPLUG_ENABLE;
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "Invert bit setting: hp_ctl:%x hp_port:%x\n",
-		    hotplug, enabled_irqs);
-	hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
-
-	/*
-	 * For BXT invert bit has to be set based on AOB design
-	 * for HPD detection logic, update it based on VBT fields.
-	 */
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
-		hotplug |= BXT_DDIA_HPD_INVERT;
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_B)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
-		hotplug |= BXT_DDIB_HPD_INVERT;
-	if ((enabled_irqs & GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)) &&
-	    intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
-		hotplug |= BXT_DDIC_HPD_INVERT;
-
+	hotplug &= ~(PORTA_HOTPLUG_ENABLE |
+		     PORTB_HOTPLUG_ENABLE |
+		     PORTC_HOTPLUG_ENABLE |
+		     BXT_DDIA_HPD_INVERT |
+		     BXT_DDIB_HPD_INVERT |
+		     BXT_DDIC_HPD_INVERT);
+	hotplug |= intel_hpd_hotplug_enables(dev_priv, bxt_hotplug_enables);
 	I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
 }
 
@@ -3403,7 +3516,7 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 	bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
 
-	bxt_hpd_detection_setup(dev_priv, enabled_irqs);
+	bxt_hpd_detection_setup(dev_priv);
 }
 
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -4116,11 +4229,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
-		if (HAS_PCH_JSP(dev_priv))
-			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
-		else if (HAS_PCH_MCC(dev_priv))
-			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
-		else if (INTEL_GEN(dev_priv) >= 11)
+		if (INTEL_GEN(dev_priv) >= 11)
 			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
 		else if (IS_GEN9_LP(dev_priv))
 			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f15914fbe7c3..9f45e8b1a43d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8442,19 +8442,6 @@ enum {
 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
 
-#define ICP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define ICP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC4) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC3) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC2) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC1))
-#define TGP_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_C) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_B) | \
-					 SHOTPLUG_CTL_DDI_HPD_ENABLE(HPD_PORT_A))
-#define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(HPD_PORT_TC6) | \
-					 ICP_TC_HPD_ENABLE(HPD_PORT_TC5) | \
-					 ICP_TC_HPD_ENABLE_MASK)
-
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
-- 
2.26.2

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (16 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 17/19] drm/i915: Enable hpd logic only for ports that are present Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 19:33   ` Lucas De Marchi
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall() Ville Syrjala
                   ` (4 subsequent siblings)
  22 siblings, 1 reply; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No reason not to use GEN3_IRQ_INIT() on icp+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 04a6f322110d..b4eddf49a62a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3713,14 +3713,10 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask = SDE_GMBUS_ICP;
 
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
-- 
2.26.2

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^ permalink raw reply related	[flat|nested] 37+ messages in thread

* Re: [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
@ 2020-10-23 19:33   ` Lucas De Marchi
  0 siblings, 0 replies; 37+ messages in thread
From: Lucas De Marchi @ 2020-10-23 19:33 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

On Fri, Oct 23, 2020 at 04:34:19PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>No reason not to use GEN3_IRQ_INIT() on icp+.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_irq.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 04a6f322110d..b4eddf49a62a 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -3713,14 +3713,10 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
>
> static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> {
>+	struct intel_uncore *uncore = &dev_priv->uncore;
> 	u32 mask = SDE_GMBUS_ICP;
>
>-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
>-	I915_WRITE(SDEIER, 0xffffffff);
>-	POSTING_READ(SDEIER);
>-
>-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
>-	I915_WRITE(SDEIMR, ~mask);
>+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> }
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
>-- 
>2.26.2
>
>_______________________________________________
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>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] [PATCH v2 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall()
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (17 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
@ 2020-10-23 13:34 ` Ville Syrjala
  2020-10-23 15:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4) Patchwork
                   ` (3 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Ville Syrjala @ 2020-10-23 13:34 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

ibx_irq_pre_postinstall() looks totally pointless. We can just
init both SDEIMR and SDEIER at the same time before enabling the
master intererupt. It's equally racy as the other order due
to doing all of this from the postinstall stage with the interrupt
handler already in place. That is, safe with MSI but racy with
shared legacy interrupts. Fortunately we should have MSI on all ilk+.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 46 ++++++++++++---------------------
 1 file changed, 17 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b4eddf49a62a..25648ea990fc 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2898,24 +2898,6 @@ static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 		I915_WRITE(SERR_INT, 0xffffffff);
 }
 
-/*
- * SDEIER is also touched by the interrupt handler to work around missed PCH
- * interrupts. Hence we can't update it after the interrupt handler is enabled -
- * instead we unconditionally enable all PCH interrupt sources here, but then
- * only unmask them as needed with SDEIMR.
- *
- * This function needs to be called before interrupts are enabled.
- */
-static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
-{
-	if (HAS_PCH_NOP(dev_priv))
-		return;
-
-	drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
-	I915_WRITE(SDEIER, 0xffffffff);
-	POSTING_READ(SDEIER);
-}
-
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3519,8 +3501,20 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
 	bxt_hpd_detection_setup(dev_priv);
 }
 
+/*
+ * SDEIER is also touched by the interrupt handler to work around missed PCH
+ * interrupts. Hence we can't update it after the interrupt handler is enabled -
+ * instead we unconditionally enable all PCH interrupt sources here, but then
+ * only unmask them as needed with SDEIMR.
+ *
+ * Note that we currently do this after installing the interrupt handler,
+ * but before we enable the master interrupt. That should be sufficient
+ * to avoid races with the irq handler, assuming we have MSI. Shared legacy
+ * interrupts could still race.
+ */
 static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 {
+	struct intel_uncore *uncore = &dev_priv->uncore;
 	u32 mask;
 
 	if (HAS_PCH_NOP(dev_priv))
@@ -3533,8 +3527,7 @@ static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
 	else
 		mask = SDE_GMBUS_CPT;
 
-	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
-	I915_WRITE(SDEIMR, ~mask);
+	GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
 }
 
 static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
@@ -3567,14 +3560,12 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	dev_priv->irq_mask = ~display_mask;
 
-	ibx_irq_pre_postinstall(dev_priv);
+	ibx_irq_postinstall(dev_priv);
 
 	gen5_gt_irq_postinstall(&dev_priv->gt);
 
 	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
 		      display_mask | extra_mask);
-
-	ibx_irq_postinstall(dev_priv);
 }
 
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3699,15 +3690,12 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 
 static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
 {
-	if (HAS_PCH_SPLIT(dev_priv))
-		ibx_irq_pre_postinstall(dev_priv);
-
-	gen8_gt_irq_postinstall(&dev_priv->gt);
-	gen8_de_irq_postinstall(dev_priv);
-
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev_priv);
 
+	gen8_gt_irq_postinstall(&dev_priv->gt);
+	gen8_de_irq_postinstall(dev_priv);
+
 	gen8_master_intr_enable(dev_priv->uncore.regs);
 }
 
-- 
2.26.2

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^ permalink raw reply related	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (18 preceding siblings ...)
  2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall() Ville Syrjala
@ 2020-10-23 15:39 ` Patchwork
  2020-10-23 15:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  22 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-23 15:39 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
477637bc8e28 drm/i915: s/PORT_TC/TC_PORT_/
-:313: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#313: FILE: drivers/gpu/drm/i915/i915_reg.h:10318:
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < TC_PORT_4 ? \
 						       (tc_port) + 12 : \
+						       (tc_port) - TC_PORT_4 + 21))

total: 0 errors, 0 warnings, 1 checks, 269 lines checked
23b37640a408 drm/i915: Add PORT_TCn aliases to enum port
30dc6119360c drm/i915: Give DDI encoders even better names
-:44: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5177:
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');

-:54: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:5187:
+				 tc_port != TC_PORT_NONE ? phy_name(phy) : tc_port - TC_PORT_1 + '1');

total: 0 errors, 2 warnings, 0 checks, 33 lines checked
7a4e10ddcf5c drm/i915: Introduce AUX_CH_USBCn
b47a0d1c69ad drm/i915: Pimp AUX CH names
4baf80bbf14f drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
e35d8538c985 drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
58b8d2bd5fc4 drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
1686173cf0ce drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
9fd957b4f19b drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
7f72a54b085a drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
d6c5f3bf0f23 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
d06518d8d0b5 drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
f36dbae0ea38 drm/i915: Don't enable hpd detection logic from irq_postinstall()
21d78326f417 drm/i915: Rename 'tmp_mask'
4364c2eaf6c4 drm/i915: Remove the per-plaform IIR HPD masking
-:68: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#68: FILE: drivers/gpu/drm/i915/i915_reg.h:8357:
+#define SDE_TC_MASK_ICP			(SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \

total: 1 errors, 0 warnings, 0 checks, 47 lines checked
f2a3021982b7 drm/i915: Enable hpd logic only for ports that are present
6acc0868abc8 drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
c0d3fbb554ac drm/i915: Get rid of ibx_irq_pre_postinstall()


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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (19 preceding siblings ...)
  2020-10-23 15:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4) Patchwork
@ 2020-10-23 15:41 ` Patchwork
  2020-10-23 16:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2020-10-23 19:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  22 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-23 15:41 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
URL   : https://patchwork.freedesktop.org/series/82411/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:100:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:101:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    expected void *in
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:136:20: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    expected void const *src
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:137:46: warning: incorrect type in argument 2 (different address spaces)
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    expected unsigned int [usertype] *s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34:    got void [noderef] __iomem *[assigned] s
+drivers/gpu/drm/i915/gt/selftest_reset.c:98:34: warning: incorrect type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 'wakeref_auto_timeout' - unexpected unlock
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (20 preceding siblings ...)
  2020-10-23 15:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-23 16:03 ` Patchwork
  2020-10-23 19:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  22 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-23 16:03 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 5922 bytes --]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
URL   : https://patchwork.freedesktop.org/series/82411/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9191 -> Patchwork_18775
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/index.html

Known issues
------------

  Here are the changes found in Patchwork_18775 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  
#### Possible fixes ####

  * igt@gem_close_race@basic-threads:
    - fi-apl-guc:         [INCOMPLETE][3] ([i915#1635]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-apl-guc/igt@gem_close_race@basic-threads.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-apl-guc/igt@gem_close_race@basic-threads.html

  * igt@i915_pm_rpm@module-reload:
    - fi-byt-j1900:       [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [DMESG-WARN][7] ([i915#165]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-kbl-7500u:       [DMESG-WARN][9] ([i915#2203]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - {fi-kbl-7560u}:     [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - fi-bsw-kefka:       [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2524]: https://gitlab.freedesktop.org/drm/intel/issues/2524


Participating hosts (46 -> 38)
------------------------------

  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bwr-2160 fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9191 -> Patchwork_18775

  CI-20190529: 20190529
  CI_DRM_9191: 4b693bbb9b41fda404b5cd081bf5cd8dba240468 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18775: c0d3fbb554ac4d111912719d4ad1f3b117d4a5cf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c0d3fbb554ac drm/i915: Get rid of ibx_irq_pre_postinstall()
6acc0868abc8 drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+
f2a3021982b7 drm/i915: Enable hpd logic only for ports that are present
4364c2eaf6c4 drm/i915: Remove the per-plaform IIR HPD masking
21d78326f417 drm/i915: Rename 'tmp_mask'
f36dbae0ea38 drm/i915: Don't enable hpd detection logic from irq_postinstall()
d06518d8d0b5 drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants
d6c5f3bf0f23 drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs()
7f72a54b085a drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits
9fd957b4f19b drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG()
1686173cf0ce drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits
58b8d2bd5fc4 drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()
e35d8538c985 drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin
4baf80bbf14f drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup
b47a0d1c69ad drm/i915: Pimp AUX CH names
7a4e10ddcf5c drm/i915: Introduce AUX_CH_USBCn
30dc6119360c drm/i915: Give DDI encoders even better names
23b37640a408 drm/i915: Add PORT_TCn aliases to enum port
477637bc8e28 drm/i915: s/PORT_TC/TC_PORT_/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/index.html

[-- Attachment #1.2: Type: text/html, Size: 7040 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
  2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
                   ` (21 preceding siblings ...)
  2020-10-23 16:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-23 19:46 ` Patchwork
  22 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2020-10-23 19:46 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 13718 bytes --]

== Series Details ==

Series: drm/i915: Futher cleanup around hpd pins and port identfiers (rev4)
URL   : https://patchwork.freedesktop.org/series/82411/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9191_full -> Patchwork_18775_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18775_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@core_hotunplug@hotrebind}:
    - shard-hsw:          NOTRUN -> [WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-hsw4/igt@core_hotunplug@hotrebind.html

  
Known issues
------------

  Here are the changes found in Patchwork_18775_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_reloc@basic-many-active@vecs0:
    - shard-glk:          [PASS][2] -> [FAIL][3] ([i915#2389]) +2 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-glk4/igt@gem_exec_reloc@basic-many-active@vecs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-glk3/igt@gem_exec_reloc@basic-many-active@vecs0.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [PASS][4] -> [DMESG-WARN][5] ([i915#1436] / [i915#716])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl2/igt@gen9_exec_parse@allowed-single.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl2/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_module_load@reload:
    - shard-tglb:         [PASS][6] -> [DMESG-WARN][7] ([i915#1982]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-tglb6/igt@i915_module_load@reload.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-tglb8/igt@i915_module_load@reload.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][8] -> [FAIL][9] ([i915#454])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge:
    - shard-glk:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-glk3/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-glk9/igt@kms_cursor_edge_walk@pipe-c-64x64-right-edge.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-hsw:          [PASS][12] -> [FAIL][13] ([i915#2370])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][14] -> [FAIL][15] ([i915#2122])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-glk3/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - shard-skl:          [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +8 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl6/igt@kms_flip@basic-plain-flip@a-edp1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl4/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_flip@flip-vs-dpms-off-vs-modeset@a-vga1:
    - shard-hsw:          [PASS][18] -> [DMESG-WARN][19] ([i915#1982])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-hsw4/igt@kms_flip@flip-vs-dpms-off-vs-modeset@a-vga1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-hsw1/igt@kms_flip@flip-vs-dpms-off-vs-modeset@a-vga1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-vga1:
    - shard-snb:          [PASS][20] -> [DMESG-WARN][21] ([i915#42])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([fdo#108145] / [i915#265])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][24] -> [SKIP][25] ([fdo#109441]) +2 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-skl:          [INCOMPLETE][26] ([i915#198]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
    - shard-skl:          [FAIL][28] ([i915#54]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][30] ([i915#180]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][32] ([i915#96]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-hsw:          [INCOMPLETE][34] ([i915#2055]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-hsw4/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
    - shard-snb:          [INCOMPLETE][36] ([i915#82]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-snb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-snb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          [DMESG-WARN][38] ([i915#1982]) -> [PASS][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-tglb:         [DMESG-WARN][40] ([i915#1982]) -> [PASS][41] +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc:
    - shard-skl:          [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +5 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [FAIL][44] ([fdo#108145] / [i915#265]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][46] ([fdo#109441]) -> [PASS][47] +1 similar issue
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [FAIL][48] ([i915#1515]) -> [WARN][49] ([i915#1515])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         [SKIP][50] ([fdo#109349]) -> [DMESG-WARN][51] ([i915#1226])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-skl:          [FAIL][52] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][53] ([fdo#108145] / [i915#1982])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
    - shard-skl:          [DMESG-FAIL][54] ([fdo#108145] / [i915#1982]) -> [FAIL][55] ([fdo#108145] / [i915#265])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9191/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
  [i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9191 -> Patchwork_18775

  CI-20190529: 20190529
  CI_DRM_9191: 4b693bbb9b41fda404b5cd081bf5cd8dba240468 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5823: 7dd2fe99bd9dde00456cc5abf7e5ef0c8d7d6118 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18775: c0d3fbb554ac4d111912719d4ad1f3b117d4a5cf @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18775/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread

end of thread, other threads:[~2020-10-28  1:00 UTC | newest]

Thread overview: 37+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-23 13:34 [Intel-gfx] [PATCH v2 00/19] drm/i915: Futher cleanup around hpd pins and port identfiers Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 01/19] drm/i915: s/PORT_TC/TC_PORT_/ Ville Syrjala
2020-10-23 17:57   ` Lucas De Marchi
2020-10-23 18:08     ` Ville Syrjälä
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 02/19] drm/i915: Add PORT_TCn aliases to enum port Ville Syrjala
2020-10-23 19:02   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 03/19] drm/i915: Give DDI encoders even better names Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 04/19] drm/i915: Introduce AUX_CH_USBCn Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 05/19] drm/i915: Pimp AUX CH names Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 06/19] drm/i915: Use AUX_CH_USBCn for the RKL VBT AUX CH setup Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 07/19] drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pin Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 08/19] drm/i915: Introduce GEN8_DE_PORT_HOTPLUG() Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 09/19] drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bits Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 10/19] drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC, TBT}_HOTPLUG() Ville Syrjala
2020-10-23 19:19   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 11/19] drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bits Ville Syrjala
2020-10-23 19:20   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 12/19] drm/i915: Relocate intel_hpd_{enabled, hotplug}_irqs() Ville Syrjala
2020-10-23 19:21   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 13/19] drm/i915: Split gen11_hpd_detection_setup() into tc vs. tbt variants Ville Syrjala
2020-10-23 19:23   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 14/19] drm/i915: Don't enable hpd detection logic from irq_postinstall() Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 15/19] drm/i915: Rename 'tmp_mask' Ville Syrjala
2020-10-23 19:25   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 16/19] drm/i915: Remove the per-plaform IIR HPD masking Ville Syrjala
2020-10-23 19:29   ` Lucas De Marchi
2020-10-23 19:44     ` Ville Syrjälä
2020-10-28  1:00       ` Lucas De Marchi
2020-10-23 19:30   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 17/19] drm/i915: Enable hpd logic only for ports that are present Ville Syrjala
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 18/19] drm/i915: Use GEN3_IRQ_INIT() to init south interrupts in icp+ Ville Syrjala
2020-10-23 19:33   ` Lucas De Marchi
2020-10-23 13:34 ` [Intel-gfx] [PATCH v2 19/19] drm/i915: Get rid of ibx_irq_pre_postinstall() Ville Syrjala
2020-10-23 15:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Futher cleanup around hpd pins and port identfiers (rev4) Patchwork
2020-10-23 15:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 16:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 19:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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