From: Ramalingam C <ramalingam.c@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, seanpaul@chromium.org
Subject: Re: [Intel-gfx] [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
Date: Thu, 5 Nov 2020 19:22:57 +0530 [thread overview]
Message-ID: <20201105135256.GE3242@intel.com> (raw)
In-Reply-To: <20201027164208.10026-5-anshuman.gupta@intel.com>
On 2020-10-27 at 22:11:56 +0530, Anshuman Gupta wrote:
> Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
> instances lies in Transcoder instead of DDI as in Gen11.
>
> This requires hdcp driver to use mst_master_transcoder for link
> authentication and stream transcoder for stream encryption
> separately.
>
> This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
> on Gen12.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> .../gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
> 5 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 63380b166c25..9fce623e951e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..c47124a679b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -432,6 +432,8 @@ struct intel_hdcp {
> * Hence caching the transcoder here.
> */
> enum transcoder cpu_transcoder;
> + /* Only used for DP MST stream encryption */
> + enum transcoder stream_transcoder;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..16865b200062 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - pipe_config->cpu_transcoder,
> + pipe_config,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b9d8825e2bb1..fc5de48456ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> }
>
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type)
> + const struct intel_crtc_state *pipe_config, u8 content_type)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
> drm_WARN_ON(&dev_priv->drm,
> hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> hdcp->content_type = content_type;
> - hdcp->cpu_transcoder = cpu_transcoder;
> +
> + if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> + hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> + hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> + } else {
> + hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> + hdcp->stream_transcoder = INVALID_TRANSCODER;
> + }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
> + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
>
> if (desired_and_not_enabled || content_protection_type_changed)
> intel_hdcp_enable(connector,
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 1bbf5b67ed0a..bc51c1e9b481 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
> int intel_hdcp_init(struct intel_connector *connector, enum port port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type);
> + const struct intel_crtc_state *pipe_config, u8 content_type);
> int intel_hdcp_disable(struct intel_connector *connector);
> void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> --
> 2.26.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com>
To: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, uma.shankar@intel.com,
seanpaul@chromium.org, juston.li@intel.com
Subject: Re: [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream
Date: Thu, 5 Nov 2020 19:22:57 +0530 [thread overview]
Message-ID: <20201105135256.GE3242@intel.com> (raw)
In-Reply-To: <20201027164208.10026-5-anshuman.gupta@intel.com>
On 2020-10-27 at 22:11:56 +0530, Anshuman Gupta wrote:
> Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
> instances lies in Transcoder instead of DDI as in Gen11.
>
> This requires hdcp driver to use mst_master_transcoder for link
> authentication and stream transcoder for stream encryption
> separately.
>
> This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
> on Gen12.
Reviewed-by: Ramalingam C <ramalingam.c@intel.com>
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> .../gpu/drm/i915/display/intel_display_types.h | 2 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
> drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
> 5 files changed, 16 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 63380b166c25..9fce623e951e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6f0626649e0..c47124a679b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -432,6 +432,8 @@ struct intel_hdcp {
> * Hence caching the transcoder here.
> */
> enum transcoder cpu_transcoder;
> + /* Only used for DP MST stream encryption */
> + enum transcoder stream_transcoder;
> };
>
> struct intel_connector {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c8fcec4d0788..16865b200062 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> if (conn_state->content_protection ==
> DRM_MODE_CONTENT_PROTECTION_DESIRED)
> intel_hdcp_enable(to_intel_connector(conn_state->connector),
> - pipe_config->cpu_transcoder,
> + pipe_config,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b9d8825e2bb1..fc5de48456ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
> }
>
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type)
> + const struct intel_crtc_state *pipe_config, u8 content_type)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> @@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
> drm_WARN_ON(&dev_priv->drm,
> hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
> hdcp->content_type = content_type;
> - hdcp->cpu_transcoder = cpu_transcoder;
> +
> + if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
> + hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
> + hdcp->stream_transcoder = pipe_config->cpu_transcoder;
> + } else {
> + hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
> + hdcp->stream_transcoder = INVALID_TRANSCODER;
> + }
>
> if (INTEL_GEN(dev_priv) >= 12)
> - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
> + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
>
> /*
> * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
> @@ -2234,7 +2241,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
>
> if (desired_and_not_enabled || content_protection_type_changed)
> intel_hdcp_enable(connector,
> - crtc_state->cpu_transcoder,
> + crtc_state,
> (u8)conn_state->hdcp_content_type);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 1bbf5b67ed0a..bc51c1e9b481 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
> int intel_hdcp_init(struct intel_connector *connector, enum port port,
> const struct intel_hdcp_shim *hdcp_shim);
> int intel_hdcp_enable(struct intel_connector *connector,
> - enum transcoder cpu_transcoder, u8 content_type);
> + const struct intel_crtc_state *pipe_config, u8 content_type);
> int intel_hdcp_disable(struct intel_connector *connector);
> void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> --
> 2.26.2
>
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2020-11-05 13:52 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 16:41 [Intel-gfx] [PATCH v4 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 01/16] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-02 7:45 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:45 ` Shankar, Uma
2020-11-05 13:18 ` [Intel-gfx] " Ramalingam C
2020-11-05 13:18 ` Ramalingam C
2020-11-05 13:21 ` [Intel-gfx] " Ramalingam C
2020-11-05 13:21 ` Ramalingam C
2020-11-05 13:26 ` Ramalingam C
2020-11-05 13:26 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 02/16] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-02 7:45 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:45 ` Shankar, Uma
2020-11-05 13:23 ` [Intel-gfx] " Ramalingam C
2020-11-05 13:23 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-06 12:00 ` [Intel-gfx] " Ramalingam C
2020-11-06 12:00 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 04/16] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-05 13:52 ` Ramalingam C [this message]
2020-11-05 13:52 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-05 13:57 ` [Intel-gfx] " Ramalingam C
2020-11-05 13:57 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 06/16] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-02 7:47 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:47 ` Shankar, Uma
2020-11-05 15:34 ` [Intel-gfx] " Ramalingam C
2020-11-05 15:34 ` Ramalingam C
2020-11-06 5:22 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 5:22 ` Anshuman Gupta
2020-11-06 7:52 ` [Intel-gfx] " Ramalingam C
2020-11-06 7:52 ` Ramalingam C
2020-10-27 16:41 ` [Intel-gfx] [PATCH v4 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2020-10-27 16:41 ` Anshuman Gupta
2020-11-02 7:47 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:47 ` Shankar, Uma
2020-11-05 15:41 ` [Intel-gfx] " Ramalingam C
2020-11-05 15:41 ` Ramalingam C
2020-11-06 6:36 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 6:36 ` Anshuman Gupta
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-05 16:39 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:39 ` Ramalingam C
2020-11-06 4:50 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 4:50 ` Anshuman Gupta
2020-11-06 7:48 ` [Intel-gfx] " Ramalingam C
2020-11-06 7:48 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-06 11:34 ` [Intel-gfx] " Ramalingam C
2020-11-06 11:34 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-05 16:07 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:07 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 11/16] drm/hdcp: Max MST content streams Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-05 16:09 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:09 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 12/16] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-02 7:49 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:49 ` Shankar, Uma
2020-11-05 16:34 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:34 ` Ramalingam C
2020-11-06 6:35 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 6:35 ` Anshuman Gupta
2020-11-06 11:28 ` [Intel-gfx] " Ramalingam C
2020-11-06 11:28 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 13/16] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-05 16:45 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:45 ` Ramalingam C
2020-11-06 5:08 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 5:08 ` Anshuman Gupta
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-05 16:47 ` [Intel-gfx] " Ramalingam C
2020-11-05 16:47 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-02 7:49 ` [Intel-gfx] " Shankar, Uma
2020-11-02 7:49 ` Shankar, Uma
2020-11-03 6:27 ` [Intel-gfx] " Anshuman Gupta
2020-11-06 9:27 ` Ramalingam C
2020-11-06 11:12 ` Ramalingam C
2020-11-09 5:36 ` Anshuman Gupta
2020-11-09 8:38 ` Ramalingam C
2020-10-27 16:42 ` [Intel-gfx] [PATCH v4 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2020-10-27 16:42 ` Anshuman Gupta
2020-11-06 11:58 ` [Intel-gfx] " Ramalingam C
2020-11-06 11:58 ` Ramalingam C
2020-10-28 2:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev2) Patchwork
2020-10-28 2:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-28 3:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-28 6:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-29 8:37 ` Anshuman Gupta
2020-10-29 22:11 ` Vudum, Lakshminarayana
2020-10-29 17:40 ` Patchwork
2020-10-29 17:54 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2020-11-02 9:02 ` Anshuman Gupta
2020-11-03 7:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev3) Patchwork
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