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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2
Date: Thu, 19 Nov 2020 17:42:18 +0200	[thread overview]
Message-ID: <20201119154218.GJ6112@intel.com> (raw)
In-Reply-To: <20201119155050.20328-2-uma.shankar@intel.com>

On Thu, Nov 19, 2020 at 09:20:49PM +0530, Uma Shankar wrote:
> There are some corner cases wrt underrun when we enable
> FBC with PSR2 on TGL. Recommendation from hardware is to
> keep this combination disabled.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Added psr2 enabled check from crtc_state (Anshuman)
> Added Bspec link and HSD referneces (Jose)
> 
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index a5b072816a7b..c64ed1cd29b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -799,6 +799,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
>  	struct intel_fbc *fbc = &dev_priv->fbc;
>  	struct intel_fbc_state_cache *cache = &fbc->state_cache;
>  
> +	/*
> +	 * Tigerlake is not supporting FBC with PSR2.
> +	 * Recommendation is to keep this combination disabled
> +	 * Bspec: 50422 HSD: 14010260002
> +	 */
> +	if (crtc->config && crtc->config->has_psr2 &&

Please don't add more crtc->config usages. After several years
we've almost reached the point where we can finally remove it.
I should porbably take a look at how much work would be required
to at least make it always NULL on g4x+.

The fbc state tracking is a total mess atm, but I think you can
stuff this into intel_fbc_update_state_cache() and either just
set cache->plane.visible=false (which is a bit of a lie but would
work), or add a new thing into the params/cache.

My plan is to eliminate most of the this params/cache mess
and just cache the things fbc really needs for hw
activate/deactivate. I do have a wip branch but haven't had
time recently to continue the work.

> +	    IS_TIGERLAKE(dev_priv)) {
> +		fbc->no_fbc_reason = "not supported with PSR2";
> +		return false;
> +	}
> +
>  	if (!intel_fbc_can_enable(dev_priv))
>  		return false;
>  
> -- 
> 2.26.2

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-11-19 15:42 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 15:50 [Intel-gfx] [v2 0/2] Re-enable FBC on TGL Uma Shankar
2020-11-19 15:50 ` [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar
2020-11-19 15:42   ` Ville Syrjälä [this message]
2020-11-19 18:54     ` Shankar, Uma
2020-11-19 19:36   ` [Intel-gfx] [v3 " Uma Shankar
2020-11-24 16:19     ` Ville Syrjälä
2020-11-24 22:03     ` Souza, Jose
2020-11-25 16:17       ` Ville Syrjälä
2020-11-25 17:52         ` Souza, Jose
2020-11-27 14:45           ` Ville Syrjälä
2020-12-01 13:56             ` Shankar, Uma
2020-11-19 15:50 ` [Intel-gfx] [v2 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar
2020-11-25 16:18   ` Ville Syrjälä
2020-11-19 17:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Re-enable FBC on TGL (rev2) Patchwork
2020-11-19 23:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL (rev3) Patchwork
2020-11-20  6:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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