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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [v3 1/2] drm/i915/display/tgl: Disable FBC with PSR2
Date: Wed, 25 Nov 2020 18:17:55 +0200	[thread overview]
Message-ID: <20201125161755.GN6112@intel.com> (raw)
In-Reply-To: <d5698ec6956ff3f0df5d3bcce9b836fcd06ef7d0.camel@intel.com>

On Tue, Nov 24, 2020 at 10:03:35PM +0000, Souza, Jose wrote:
> On Fri, 2020-11-20 at 01:06 +0530, Uma Shankar wrote:
> > There are some corner cases wrt underrun when we enable
> > FBC with PSR2 on TGL. Recommendation from hardware is to
> > keep this combination disabled.
> > 
> > Bspec: 50422 HSD: 14010260002
> > 
> > v2: Added psr2 enabled check from crtc_state (Anshuman)
> > Added Bspec link and HSD referneces (Jose)
> > 
> > v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
> > and removed the crtc->config usages, as per Ville's recommendation.
> > 
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index a5b072816a7b..cb29c6f068f9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -701,6 +701,15 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
> >  	struct drm_framebuffer *fb = plane_state->hw.fb;
> >  
> > 
> > 
> > 
> >  	cache->plane.visible = plane_state->uapi.visible;
> > +
> > +	/*
> > +	 * Tigerlake is not supporting FBC with PSR2.
> > +	 * Recommendation is to keep this combination disabled
> > +	 * Bspec: 50422 HSD: 14010260002
> > +	 */
> > +	if (crtc_state->has_psr2 && IS_TIGERLAKE(dev_priv))
> > +		cache->plane.visible = false;
> 
> Looks like a hack to me, would be better add a psr2 variable in intel_fbc_state_cache.

The plan is to remove most things from that cache anyway since it's
mostly pointless stuff that should just be handled directly via
the plane/crtc states. Not really convinced it makes sense to add
more crap to it at this time. So IMO this is good enough for now.

> We also would need have a PSR2 reason set in no_fbc_reason and handle it in IGT.

I think that no_fbc_reason is rather pointless as well. Would make
life a lot simpler if we didn't have to worry about it. So tempted
to just nuke it.

> 
> > +
> >  	if (!cache->plane.visible)
> >  		return;
> >  
> > 
> > 
> > 
> 

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2020-11-25 16:18 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 15:50 [Intel-gfx] [v2 0/2] Re-enable FBC on TGL Uma Shankar
2020-11-19 15:50 ` [Intel-gfx] [v2 1/2] drm/i915/display/tgl: Disable FBC with PSR2 Uma Shankar
2020-11-19 15:42   ` Ville Syrjälä
2020-11-19 18:54     ` Shankar, Uma
2020-11-19 19:36   ` [Intel-gfx] [v3 " Uma Shankar
2020-11-24 16:19     ` Ville Syrjälä
2020-11-24 22:03     ` Souza, Jose
2020-11-25 16:17       ` Ville Syrjälä [this message]
2020-11-25 17:52         ` Souza, Jose
2020-11-27 14:45           ` Ville Syrjälä
2020-12-01 13:56             ` Shankar, Uma
2020-11-19 15:50 ` [Intel-gfx] [v2 2/2] Revert "drm/i915/display/fbc: Disable fbc by default on TGL" Uma Shankar
2020-11-25 16:18   ` Ville Syrjälä
2020-11-19 17:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Re-enable FBC on TGL (rev2) Patchwork
2020-11-19 23:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Re-enable FBC on TGL (rev3) Patchwork
2020-11-20  6:13 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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