From: Rob Herring <robh@kernel.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: devicetree@vger.kernel.org, Conor.Dooley@microchip.com,
Anup Patel <anup.patel@wdc.com>,
Cyril.Jean@microchip.com,
Daire McNamara <daire.mcnamara@microchip.com>,
Bin Meng <bin.meng@windriver.com>,
linux-kernel@vger.kernel.org, Ivan.Griffin@microchip.com,
Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <alistair.francis@wdc.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC
Date: Wed, 9 Dec 2020 17:30:11 -0600 [thread overview]
Message-ID: <20201209233011.GA1276461@robh.at.kernel.org> (raw)
In-Reply-To: <20201204085835.2406541-3-atish.patra@wdc.com>
On Fri, Dec 04, 2020 at 12:58:32AM -0800, Atish Patra wrote:
> Add YAML DT binding documentation for the Microchip PolarFire SoC.
> It is documented at:
>
> https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> new file mode 100644
> index 000000000000..66e63c2bf359
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR MIT)
See what checkpatch.pl says.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/microchip.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire SoC-based boards device tree bindings
> +
> +maintainers:
> + - Cyril Jean <Cyril.Jean@microchip.com>
> + - Lewis Hanly <lewis.hanly@microchip.com>
> +
> +description:
> + Microchip PolarFire SoC-based boards
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + items:
> + - enum:
> + - microchip,mpfs-icicle-kit
> + - const: microchip,polarfire-soc
> + - const: microchip,mpfs
Is this last compatible really useful? Usually better to just have SoC
and board (or SoM plus baseboard) compatibles.
Rob
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WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Atish Patra <atish.patra@wdc.com>
Cc: linux-kernel@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
Alistair Francis <alistair.francis@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Ivan.Griffin@microchip.com, Cyril.Jean@microchip.com,
Daire McNamara <daire.mcnamara@microchip.com>,
Conor.Dooley@microchip.com
Subject: Re: [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC
Date: Wed, 9 Dec 2020 17:30:11 -0600 [thread overview]
Message-ID: <20201209233011.GA1276461@robh.at.kernel.org> (raw)
In-Reply-To: <20201204085835.2406541-3-atish.patra@wdc.com>
On Fri, Dec 04, 2020 at 12:58:32AM -0800, Atish Patra wrote:
> Add YAML DT binding documentation for the Microchip PolarFire SoC.
> It is documented at:
>
> https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> .../devicetree/bindings/riscv/microchip.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> new file mode 100644
> index 000000000000..66e63c2bf359
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -0,0 +1,28 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR MIT)
See what checkpatch.pl says.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/microchip.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire SoC-based boards device tree bindings
> +
> +maintainers:
> + - Cyril Jean <Cyril.Jean@microchip.com>
> + - Lewis Hanly <lewis.hanly@microchip.com>
> +
> +description:
> + Microchip PolarFire SoC-based boards
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + items:
> + - enum:
> + - microchip,mpfs-icicle-kit
> + - const: microchip,polarfire-soc
> + - const: microchip,mpfs
Is this last compatible really useful? Usually better to just have SoC
and board (or SoM plus baseboard) compatibles.
Rob
next prev parent reply other threads:[~2020-12-09 23:30 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra
2020-12-04 8:58 ` Atish Patra
2020-12-04 8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-12-04 8:58 ` Atish Patra
2021-01-07 11:39 ` Cyril.Jean
2021-01-07 11:39 ` Cyril.Jean
2021-01-07 19:21 ` Atish Patra
2021-01-07 19:21 ` Atish Patra
2020-12-04 8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra
2020-12-04 8:58 ` Atish Patra
2020-12-09 23:30 ` Rob Herring [this message]
2020-12-09 23:30 ` Rob Herring
2020-12-04 8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-12-04 8:58 ` Atish Patra
2020-12-10 11:06 ` Bin Meng
2020-12-10 11:06 ` Bin Meng
2021-01-07 11:43 ` Cyril.Jean
2021-01-07 11:43 ` Cyril.Jean
2021-01-07 19:26 ` Atish Patra
2021-01-07 19:26 ` Atish Patra
2020-12-04 8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-12-04 8:58 ` Atish Patra
2020-12-26 0:37 ` Aurelien Jarno
2020-12-26 0:37 ` Aurelien Jarno
2020-12-04 8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra
2020-12-04 8:58 ` Atish Patra
2020-12-10 11:08 ` Bin Meng
2020-12-10 11:08 ` Bin Meng
2020-12-22 3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-12-22 3:19 ` Palmer Dabbelt
2020-12-22 20:14 ` Atish Patra
2020-12-22 20:14 ` Atish Patra
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