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From: Aurelien Jarno <aurelien@aurel32.net>
To: Atish Patra <atish.patra@wdc.com>
Cc: devicetree@vger.kernel.org, Anup Patel <anup.patel@wdc.com>,
	Cyril.Jean@microchip.com,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Anup Patel <anup@brainfault.org>,
	Bin Meng <bin.meng@windriver.com>,
	linux-kernel@vger.kernel.org, Conor.Dooley@microchip.com,
	Rob Herring <robh+dt@kernel.org>,
	Ivan.Griffin@microchip.com,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	linux-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Subject: Re: [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC
Date: Sat, 26 Dec 2020 01:37:54 +0100	[thread overview]
Message-ID: <X+aF4q8RyayzTNk3@aurel32.net> (raw)
In-Reply-To: <20201204085835.2406541-5-atish.patra@wdc.com>

On 2020-12-04 00:58, Atish Patra wrote:
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
> 
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
>  arch/riscv/configs/defconfig | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
>  CONFIG_BPF_SYSCALL=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_SMP=y
>  CONFIG_JUMP_LABEL=y
>  CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
>  CONFIG_USB_OHCI_HCD_PLATFORM=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y

I guess this should be CONFIG_MMC_SDHCI=y

> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
>  CONFIG_MMC=y
>  CONFIG_MMC_SPI=y
>  CONFIG_RTC_CLASS=y

Regards,
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

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WARNING: multiple messages have this Message-ID (diff)
From: Aurelien Jarno <aurelien@aurel32.net>
To: Atish Patra <atish.patra@wdc.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	Bin Meng <bin.meng@windriver.com>,
	Cyril.Jean@microchip.com,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Anup Patel <anup@brainfault.org>, Anup Patel <anup.patel@wdc.com>,
	Conor.Dooley@microchip.com, Rob Herring <robh+dt@kernel.org>,
	Ivan.Griffin@microchip.com, Albert Ou <aou@eecs.berkeley.edu>,
	Alistair Francis <alistair.francis@wdc.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC
Date: Sat, 26 Dec 2020 01:37:54 +0100	[thread overview]
Message-ID: <X+aF4q8RyayzTNk3@aurel32.net> (raw)
In-Reply-To: <20201204085835.2406541-5-atish.patra@wdc.com>

On 2020-12-04 00:58, Atish Patra wrote:
> Enable Microchip PolarFire ICICLE soc config in defconfig.
> It allows the default upstream kernel to boot on PolarFire ICICLE board.
> 
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
>  arch/riscv/configs/defconfig | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d222d353d86d..2660fa05451e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -16,6 +16,7 @@ CONFIG_EXPERT=y
>  CONFIG_BPF_SYSCALL=y
>  CONFIG_SOC_SIFIVE=y
>  CONFIG_SOC_VIRT=y
> +CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_SMP=y
>  CONFIG_JUMP_LABEL=y
>  CONFIG_MODULES=y
> @@ -79,6 +80,9 @@ CONFIG_USB_OHCI_HCD=y
>  CONFIG_USB_OHCI_HCD_PLATFORM=y
>  CONFIG_USB_STORAGE=y
>  CONFIG_USB_UAS=y
> +CONFIG_SDHCI=y

I guess this should be CONFIG_MMC_SDHCI=y

> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_CADENCE=y
>  CONFIG_MMC=y
>  CONFIG_MMC_SPI=y
>  CONFIG_RTC_CLASS=y

Regards,
Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

  reply	other threads:[~2020-12-26  0:38 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-04  8:58 [PATCH v3 0/5] Add Microchip PolarFire Soc Support Atish Patra
2020-12-04  8:58 ` Atish Patra
2020-12-04  8:58 ` [PATCH v3 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra
2020-12-04  8:58   ` Atish Patra
2021-01-07 11:39   ` Cyril.Jean
2021-01-07 11:39     ` Cyril.Jean
2021-01-07 19:21     ` Atish Patra
2021-01-07 19:21       ` Atish Patra
2020-12-04  8:58 ` [PATCH v3 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra
2020-12-04  8:58   ` Atish Patra
2020-12-09 23:30   ` Rob Herring
2020-12-09 23:30     ` Rob Herring
2020-12-04  8:58 ` [PATCH v3 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra
2020-12-04  8:58   ` Atish Patra
2020-12-10 11:06   ` Bin Meng
2020-12-10 11:06     ` Bin Meng
2021-01-07 11:43   ` Cyril.Jean
2021-01-07 11:43     ` Cyril.Jean
2021-01-07 19:26     ` Atish Patra
2021-01-07 19:26       ` Atish Patra
2020-12-04  8:58 ` [PATCH v3 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra
2020-12-04  8:58   ` Atish Patra
2020-12-26  0:37   ` Aurelien Jarno [this message]
2020-12-26  0:37     ` Aurelien Jarno
2020-12-04  8:58 ` [PATCH v3 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra
2020-12-04  8:58   ` Atish Patra
2020-12-10 11:08   ` Bin Meng
2020-12-10 11:08     ` Bin Meng
2020-12-22  3:19 ` [PATCH v3 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt
2020-12-22  3:19   ` Palmer Dabbelt
2020-12-22 20:14   ` Atish Patra
2020-12-22 20:14     ` Atish Patra

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