From: Samuel Thibault <samuel.thibault@ens-lyon.org>
To: Keith Busch <kbusch@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,
linux-nvme@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: Are AER corrected errors worrying?
Date: Mon, 4 Jan 2021 23:33:13 +0100 [thread overview]
Message-ID: <20210104223313.plaaph3erefjw3rd@function> (raw)
In-Reply-To: <20210104213648.enkuq5e2o6adbiur@function>
Samuel Thibault, le lun. 04 janv. 2021 22:36:48 +0100, a ecrit:
> Samuel Thibault, le lun. 04 janv. 2021 21:12:47 +0100, a ecrit:
> > Keith Busch, le lun. 04 janv. 2021 10:44:35 -0800, a ecrit:
> > > PCI also has automatic link power savings that you can disable with
> > > parameter "pcie_aspm=off".
> >
> > I'll try that if I still see errors with the nvme_core parameter.
>
> I'm on it.
(FTR It switched these lines)
02:00.0 Non-Volatile memory controller: Sandisk Corp WD Black SN750 / PC SN730 NVMe SSD (prog-if 02 [NVM Express])
[...]
Capabilities: [c0] Express (v2) Endpoint, MSI 00
[...]
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
-> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
-> DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
[...]
Capabilities: [100 v2] Advanced Error Reporting
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
-> CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
[...]
Capabilities: [900 v1] L1 PM Substates
[...]
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
T_CommonMode=0us LTR1.2_Threshold=163840ns
-> T_CommonMode=0us LTR1.2_Threshold=81920ns
Samuel
_______________________________________________
Linux-nvme mailing list
Linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Thibault <samuel.thibault@ens-lyon.org>
To: Keith Busch <kbusch@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,
linux-nvme@lists.infradead.org, linux-pci@vger.kernel.org
Subject: Re: Are AER corrected errors worrying?
Date: Mon, 4 Jan 2021 23:33:13 +0100 [thread overview]
Message-ID: <20210104223313.plaaph3erefjw3rd@function> (raw)
In-Reply-To: <20210104213648.enkuq5e2o6adbiur@function>
Samuel Thibault, le lun. 04 janv. 2021 22:36:48 +0100, a ecrit:
> Samuel Thibault, le lun. 04 janv. 2021 21:12:47 +0100, a ecrit:
> > Keith Busch, le lun. 04 janv. 2021 10:44:35 -0800, a ecrit:
> > > PCI also has automatic link power savings that you can disable with
> > > parameter "pcie_aspm=off".
> >
> > I'll try that if I still see errors with the nvme_core parameter.
>
> I'm on it.
(FTR It switched these lines)
02:00.0 Non-Volatile memory controller: Sandisk Corp WD Black SN750 / PC SN730 NVMe SSD (prog-if 02 [NVM Express])
[...]
Capabilities: [c0] Express (v2) Endpoint, MSI 00
[...]
DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq+
-> DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
-> DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
[...]
Capabilities: [100 v2] Advanced Error Reporting
CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
-> CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+
[...]
Capabilities: [900 v1] L1 PM Substates
[...]
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1-
T_CommonMode=0us LTR1.2_Threshold=163840ns
-> T_CommonMode=0us LTR1.2_Threshold=81920ns
Samuel
next prev parent reply other threads:[~2021-01-04 22:33 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-01 22:40 Are AER corrected errors worrying? Samuel Thibault
2021-01-04 18:44 ` Keith Busch
2021-01-04 20:12 ` Samuel Thibault
2021-01-04 20:12 ` Samuel Thibault
2021-01-04 21:36 ` Samuel Thibault
2021-01-04 21:36 ` Samuel Thibault
2021-01-04 22:33 ` Samuel Thibault [this message]
2021-01-04 22:33 ` Samuel Thibault
2021-01-06 20:28 ` Samuel Thibault
2021-01-06 20:28 ` Samuel Thibault
2021-01-06 21:48 ` Keith Busch
2021-01-06 21:48 ` Keith Busch
2021-01-06 22:40 ` Samuel Thibault
2021-01-06 22:40 ` Samuel Thibault
-- strict thread matches above, loose matches on Subject: below --
2021-01-02 17:03 Samuel Thibault
2021-01-03 6:45 ` Vidya Sagar
2021-01-03 11:25 ` Samuel Thibault
2021-01-03 13:48 ` Samuel Thibault
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210104223313.plaaph3erefjw3rd@function \
--to=samuel.thibault@ens-lyon.org \
--cc=kbusch@kernel.org \
--cc=linux-nvme@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=vidyas@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.