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From: "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: igt-dev@lists.freedesktop.org
Subject: Re: [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields
Date: Fri, 14 May 2021 12:51:47 +0300	[thread overview]
Message-ID: <20210514095147.GC8652@intel.com> (raw)
In-Reply-To: <20210414022754.31710-9-ville.syrjala@linux.intel.com>

On Wed, Apr 14, 2021 at 05:27:54AM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Modern platforms have more bits in the registers. Deal with it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@gmail.com>

> ---
>  tools/intel_watermark.c | 32 ++++++++++++++++----------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index f5613c333dc3..1e235ed30a63 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -471,8 +471,8 @@ static void skl_wm_dump(void)
>  		for (level = 0; level < num_levels; level++) {
>  			printf("%10d", level);
>  			for (plane = 0; plane < num_planes; plane++) {
> -				blocks = REG_DECODE1(wm[level][pipe][plane], 0, 11);
> -				lines = REG_DECODE1(wm[level][pipe][plane], 14, 5);
> +				blocks = REG_DECODE1(wm[level][pipe][plane], 0, 12);
> +				lines = REG_DECODE1(wm[level][pipe][plane], 14, 13);
>  				enable = REG_DECODE1(wm[level][pipe][plane], 31, 1);
>  
>  				printf("%5d%c", blocks, endis_ast(enable));
> @@ -486,8 +486,8 @@ static void skl_wm_dump(void)
>  
>  		printf("     TRANS");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 11);
> -			lines = REG_DECODE1(wm_trans[pipe][plane], 14, 5);
> +			blocks = REG_DECODE1(wm_trans[pipe][plane], 0, 12);
> +			lines = REG_DECODE1(wm_trans[pipe][plane], 14, 13);
>  			enable = REG_DECODE1(wm_trans[pipe][plane], 31, 1);
>  
>  			printf("%5d%c", blocks, endis_ast(enable));
> @@ -500,8 +500,8 @@ static void skl_wm_dump(void)
>  		if (skl_has_sagv_wm(devid)) {
>  			printf("\n      SAGV");
>  			for (plane = 0; plane < num_planes; plane++) {
> -				blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 11);
> -				lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 5);
> +				blocks = REG_DECODE1(wm_sagv[pipe][plane], 0, 12);
> +				lines = REG_DECODE1(wm_sagv[pipe][plane], 14, 13);
>  				enable = REG_DECODE1(wm_sagv[pipe][plane], 31, 1);
>  
>  				printf("%5d%c", blocks, endis_ast(enable));
> @@ -513,8 +513,8 @@ static void skl_wm_dump(void)
>  
>  			printf("\nSAGV TRANS");
>  			for (plane = 0; plane < num_planes; plane++) {
> -				blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 11);
> -				lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 5);
> +				blocks = REG_DECODE1(wm_sagv_trans[pipe][plane], 0, 12);
> +				lines = REG_DECODE1(wm_sagv_trans[pipe][plane], 14, 13);
>  				enable = REG_DECODE1(wm_sagv_trans[pipe][plane], 31, 1);
>  
>  				printf("%5d%c", blocks, endis_ast(enable));
> @@ -529,20 +529,20 @@ static void skl_wm_dump(void)
>  
>  		printf("\nstart");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
> +			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
>  			printf("%10d", start);
>  		}
>  
>  		printf("\n  end");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			end = REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
> +			end = REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
>  			printf("%10d", end);
>  		}
>  
>  		printf("\n size");
>  		for (plane = 0; plane < num_planes; plane++) {
> -			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 11);
> -			end =  REG_DECODE1(buf_cfg[pipe][plane], 16, 11);
> +			start = REG_DECODE1(buf_cfg[pipe][plane], 0, 12);
> +			end =  REG_DECODE1(buf_cfg[pipe][plane], 16, 12);
>  			size = end - start + 1;
>  			printf("%10d", (end == 0 && size == 1) ? 0 : size);
>  		}
> @@ -553,20 +553,20 @@ static void skl_wm_dump(void)
>  
>  			printf("\nstart");
>  			for (plane = 0; plane < num_planes; plane++) {
> -				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> +				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
>  				printf("%10d", start);
>  			}
>  
>  			printf("\n  end");
>  			for (plane = 0; plane < num_planes; plane++) {
> -				end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> +				end = REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
>  				printf("%10d", end);
>  			}
>  
>  			printf("\n size");
>  			for (plane = 0; plane < num_planes; plane++) {
> -				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 11);
> -				end =  REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 11);
> +				start = REG_DECODE1(nv12_buf_cfg[pipe][plane], 0, 12);
> +				end =  REG_DECODE1(nv12_buf_cfg[pipe][plane], 16, 12);
>  				size = end - start + 1;
>  				printf("%10d", (end == 0 && size == 1) ? 0 : size);
>  			}
> -- 
> 2.26.3
> 
> _______________________________________________
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  reply	other threads:[~2021-05-14  9:48 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  2:27 [igt-dev] [PATCH i-g-t 0/8] tools/intel_watermark: Support new platofrms Ville Syrjala
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 1/8] tools/intel_watermark: Parse WM_DBG to help diagnose watermark issues Ville Syrjala
2021-05-14  9:31   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 2/8] tools/intel_watermark: Use WM_SR_CNT to observe SR residency Ville Syrjala
2021-05-14  9:36   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 3/8] tools/intel_watermark: Deal with TGL planes Ville Syrjala
2021-05-14  9:47   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 4/8] tools/intel_watermark: Reduce the number of planes for rkl/adls/adlp Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 5/8] tools/intel_watermark: TGL+ can have 4 pipes Ville Syrjala
2021-05-14  9:53   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 6/8] tools/intel_watermark: Make reg dump section less wide Ville Syrjala
2021-05-14  9:50   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 7/8] tools/intel_watermark: Handle ADL-P dedicated SAGV watermarks Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav
2021-04-14  2:27 ` [igt-dev] [PATCH i-g-t 8/8] tools/intel_watermark: Widen register bitfields Ville Syrjala
2021-05-14  9:51   ` Lisovskiy, Stanislav [this message]
2021-04-14  3:04 ` [igt-dev] ✓ Fi.CI.BAT: success for tools/intel_watermark: Support new platofrms Patchwork
2021-04-14  4:01 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork

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