* [PATCH v1 1/3] lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
2021-06-07 4:33 [PATCH v1 0/3] lpc32xx updates Trevor Woerner
@ 2021-06-07 4:33 ` Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 2/3] lpc32xx: import device tree from Linux Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 3/3] arm: lpc32xx: add EA LPC3250 DevKitv2 board support Trevor Woerner
2 siblings, 0 replies; 4+ messages in thread
From: Trevor Woerner @ 2021-06-07 4:33 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Vladimir Zapolskiy, Albert ARIBAUD, Simon Glass, Adam Ford,
Stefan Roese, Patrick Delaunay, Michal Simek
There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
---
arch/arm/include/asm/arch-lpc32xx/config.h | 4 ++--
arch/arm/mach-lpc32xx/devices.c | 3 +--
board/timll/devkit3250/devkit3250.c | 2 +-
board/timll/devkit3250/devkit3250_spl.c | 2 +-
board/work-microwave/work_92105/work_92105.c | 2 +-
board/work-microwave/work_92105/work_92105_spl.c | 2 +-
configs/devkit3250_defconfig | 2 ++
configs/work_92105_defconfig | 2 ++
include/configs/devkit3250.h | 5 -----
include/configs/work_92105.h | 5 -----
scripts/config_whitelist.txt | 1 -
11 files changed, 11 insertions(+), 19 deletions(-)
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 0836091af2..45e46f9946 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -12,8 +12,8 @@
/* Basic CPU architecture */
/* UART configuration */
-#if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
- (CONFIG_SYS_LPC32XX_UART == 7)
+#if (CONFIG_CONS_INDEX == 1) || (CONFIG_CONS_INDEX == 2) || \
+ (CONFIG_CONS_INDEX == 7)
#if !defined(CONFIG_LPC32XX_HSUART)
#define CONFIG_LPC32XX_HSUART
#endif
diff --git a/arch/arm/mach-lpc32xx/devices.c b/arch/arm/mach-lpc32xx/devices.c
index e1e2e0d094..0a4fef295a 100644
--- a/arch/arm/mach-lpc32xx/devices.c
+++ b/arch/arm/mach-lpc32xx/devices.c
@@ -23,8 +23,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
return;
/* Disable loopback mode, if it is set by S1L bootloader */
- clrbits_le32(&ctrl->loop,
- UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
+ clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
if (uart_id < 3 || uart_id > 6)
return;
diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c
index 3c744b943f..9d4ffb0f97 100644
--- a/board/timll/devkit3250/devkit3250.c
+++ b/board/timll/devkit3250/devkit3250.c
@@ -38,7 +38,7 @@ void reset_periph(void)
int board_early_init_f(void)
{
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
lpc32xx_i2c_init(1);
lpc32xx_i2c_init(2);
lpc32xx_ssp_init();
diff --git a/board/timll/devkit3250/devkit3250_spl.c b/board/timll/devkit3250/devkit3250_spl.c
index 47af78ae0b..12e8ae9c39 100644
--- a/board/timll/devkit3250/devkit3250_spl.c
+++ b/board/timll/devkit3250/devkit3250_spl.c
@@ -49,7 +49,7 @@ void spl_board_init(void)
/* First of all silence buzzer controlled by GPO_20 */
writel((1 << 20), &gpio->p3_outp_clr);
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
preloader_console_init();
ddr_init(&dram_64mb);
diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c
index bdcecff730..5d12f84cfe 100644
--- a/board/work-microwave/work_92105/work_92105.c
+++ b/board/work-microwave/work_92105/work_92105.c
@@ -37,7 +37,7 @@ void reset_periph(void)
int board_early_init_f(void)
{
/* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
/* enable I2C, SSP, MAC, NAND */
lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
lpc32xx_ssp_init();
diff --git a/board/work-microwave/work_92105/work_92105_spl.c b/board/work-microwave/work_92105/work_92105_spl.c
index a31553a2d2..d9401145f2 100644
--- a/board/work-microwave/work_92105/work_92105_spl.c
+++ b/board/work-microwave/work_92105/work_92105_spl.c
@@ -58,7 +58,7 @@ const struct emc_dram_settings dram_128mb = {
void spl_board_init(void)
{
/* initialize serial port for console */
- lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
/* initialize console */
preloader_console_init();
/* init DDR and NAND to chainload U-Boot */
diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig
index 93c048cee8..9ae70f7d46 100644
--- a/configs/devkit3250_defconfig
+++ b/configs/devkit3250_defconfig
@@ -51,6 +51,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ADDR=31
CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_USB=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index c3f666dcfe..e9605adedd 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -48,5 +48,7 @@ CONFIG_MTD_RAW_NAND=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 5d2b77b4a3..921a38c01e 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -30,11 +30,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- GENERATED_GBL_DATA_SIZE)
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
-
/*
* DMA
*/
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index 7874b77f3f..076a1b065e 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -35,11 +35,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
- GENERATED_GBL_DATA_SIZE)
-/*
- * Serial Driver
- */
-#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
-
/*
* Ethernet Driver
*/
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 8f92b82719..00a58d65fc 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2737,7 +2737,6 @@ CONFIG_SYS_LOW
CONFIG_SYS_LOWMEM_BASE
CONFIG_SYS_LOW_RES_TIMER
CONFIG_SYS_LPAE_SDRAM_BASE
-CONFIG_SYS_LPC32XX_UART
CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH
CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS
--
2.30.0.rc0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v1 2/3] lpc32xx: import device tree from Linux
2021-06-07 4:33 [PATCH v1 0/3] lpc32xx updates Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 1/3] lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX Trevor Woerner
@ 2021-06-07 4:33 ` Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 3/3] arm: lpc32xx: add EA LPC3250 DevKitv2 board support Trevor Woerner
2 siblings, 0 replies; 4+ messages in thread
From: Trevor Woerner @ 2021-06-07 4:33 UTC (permalink / raw)
To: U-Boot Mailing List
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board
directly and unmodified from the latest Linux kernel.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
---
arch/arm/dts/lpc3250-ea3250.dts | 273 ++++++++++++
arch/arm/dts/lpc32xx.dtsi | 508 ++++++++++++++++++++++
include/dt-bindings/clock/lpc32xx-clock.h | 58 +++
3 files changed, 839 insertions(+)
create mode 100644 arch/arm/dts/lpc3250-ea3250.dts
create mode 100644 arch/arm/dts/lpc32xx.dtsi
create mode 100644 include/dt-bindings/clock/lpc32xx-clock.h
diff --git a/arch/arm/dts/lpc3250-ea3250.dts b/arch/arm/dts/lpc3250-ea3250.dts
new file mode 100644
index 0000000000..63c6f17bb7
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+/dts-v1/;
+#include "lpc32xx.dtsi"
+
+/ {
+ model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+ compatible = "ea,ea3250", "nxp,lpc3250";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ button {
+ label = "Interrupt Key";
+ linux,code = <103>;
+ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+ };
+
+ key1 {
+ label = "KEY1";
+ linux,code = <1>;
+ gpios = <&pca9532 0 0>;
+ };
+
+ key2 {
+ label = "KEY2";
+ linux,code = <2>;
+ gpios = <&pca9532 1 0>;
+ };
+
+ key3 {
+ label = "KEY3";
+ linux,code = <3>;
+ gpios = <&pca9532 2 0>;
+ };
+
+ key4 {
+ label = "KEY4";
+ linux,code = <4>;
+ gpios = <&pca9532 3 0>;
+ };
+
+ joy0 {
+ label = "Joystick Key 0";
+ linux,code = <10>;
+ gpios = <&gpio 2 0 0>; /* P2.0 */
+ };
+
+ joy1 {
+ label = "Joystick Key 1";
+ linux,code = <11>;
+ gpios = <&gpio 2 1 0>; /* P2.1 */
+ };
+
+ joy2 {
+ label = "Joystick Key 2";
+ linux,code = <12>;
+ gpios = <&gpio 2 2 0>; /* P2.2 */
+ };
+
+ joy3 {
+ label = "Joystick Key 3";
+ linux,code = <13>;
+ gpios = <&gpio 2 3 0>; /* P2.3 */
+ };
+
+ joy4 {
+ label = "Joystick Key 4";
+ linux,code = <14>;
+ gpios = <&gpio 2 4 0>; /* P2.4 */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* LEDs on OEM Board */
+
+ led1 {
+ gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+ linux,default-trigger = "timer";
+ default-state = "off";
+ };
+
+ led2 {
+ gpios = <&gpio 2 10 1>; /* P2.10, active low */
+ default-state = "off";
+ };
+
+ led3 {
+ gpios = <&gpio 2 11 1>; /* P2.11, active low */
+ default-state = "off";
+ };
+
+ led4 {
+ gpios = <&gpio 2 12 1>; /* P2.12, active low */
+ default-state = "off";
+ };
+
+ /* LEDs on Base Board */
+
+ lede1 {
+ gpios = <&pca9532 8 0>;
+ default-state = "off";
+ };
+ lede2 {
+ gpios = <&pca9532 9 0>;
+ default-state = "off";
+ };
+ lede3 {
+ gpios = <&pca9532 10 0>;
+ default-state = "off";
+ };
+ lede4 {
+ gpios = <&pca9532 11 0>;
+ default-state = "off";
+ };
+ lede5 {
+ gpios = <&pca9532 12 0>;
+ default-state = "off";
+ };
+ lede6 {
+ gpios = <&pca9532 13 0>;
+ default-state = "off";
+ };
+ lede7 {
+ gpios = <&pca9532 14 0>;
+ default-state = "off";
+ };
+ lede8 {
+ gpios = <&pca9532 15 0>;
+ default-state = "off";
+ };
+ };
+};
+
+/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+&adc {
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+
+ uda1380: uda1380@18 {
+ compatible = "nxp,uda1380";
+ reg = <0x18>;
+ power-gpio = <&gpio 3 10 0>;
+ reset-gpio = <&gpio 3 2 0>;
+ dac-clk = "wspll";
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+
+ pca9532: pca9532@60 {
+ compatible = "nxp,pca9532";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x60>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+};
+
+&i2cusb {
+ clock-frequency = <100000>;
+
+ isp1301: usb-transceiver@2d {
+ compatible = "nxp,isp1301";
+ reg = <0x2d>;
+ };
+};
+
+&mac {
+ phy-mode = "rmii";
+ use-iram;
+ status = "okay";
+};
+
+/* Here, choose exactly one from: ohci, usbd */
+&ohci /* &usbd */ {
+ transceiver = <&isp1301>;
+ status = "okay";
+};
+
+&sd {
+ wp-gpios = <&pca9532 5 0>;
+ cd-gpios = <&pca9532 4 0>;
+ cd-inverted;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* 128MB Flash via SLC NAND controller */
+&slc {
+ status = "okay";
+
+ nxp,wdr-clks = <14>;
+ nxp,wwidth = <260000000>;
+ nxp,whold = <104000000>;
+ nxp,wsetup = <200000000>;
+ nxp,rdr-clks = <14>;
+ nxp,rwidth = <34666666>;
+ nxp,rhold = <104000000>;
+ nxp,rsetup = <200000000>;
+ nand-on-flash-bbt;
+ gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mtd0@0 {
+ label = "ea3250-boot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+
+ mtd1@80000 {
+ label = "ea3250-uboot";
+ reg = <0x00080000 0x000c0000>;
+ read-only;
+ };
+
+ mtd2@140000 {
+ label = "ea3250-kernel";
+ reg = <0x00140000 0x00400000>;
+ };
+
+ mtd3@540000 {
+ label = "ea3250-rootfs";
+ reg = <0x00540000 0x07ac0000>;
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart6 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/lpc32xx.dtsi b/arch/arm/dts/lpc32xx.dtsi
new file mode 100644
index 0000000000..c87066d6c9
--- /dev/null
+++ b/arch/arm/dts/lpc32xx.dtsi
@@ -0,0 +1,508 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * NXP LPC32xx SoC
+ *
+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ */
+
+#include <dt-bindings/clock/lpc32xx-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "nxp,lpc3220";
+ interrupt-parent = <&mic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0x0>;
+ };
+ };
+
+ clocks {
+ xtal_32k: xtal_32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32k";
+ };
+
+ xtal: xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13000000>;
+ clock-output-names = "xtal";
+ };
+ };
+
+ ahb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x00000000 0x10000000>,
+ <0x20000000 0x20000000 0x30000000>,
+ <0xe0000000 0xe0000000 0x04000000>;
+
+ iram: sram@8000000 {
+ compatible = "mmio-sram";
+ reg = <0x08000000 0x20000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x08000000 0x20000>;
+ };
+
+ /*
+ * Enable either SLC or MLC
+ */
+ slc: flash@20020000 {
+ compatible = "nxp,lpc3220-slc";
+ reg = <0x20020000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SLC>;
+ status = "disabled";
+ };
+
+ mlc: flash@200a8000 {
+ compatible = "nxp,lpc3220-mlc";
+ reg = <0x200a8000 0x11000>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_MLC>;
+ status = "disabled";
+ };
+
+ dma: dma@31000000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x31000000 0x1000>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_DMA>;
+ clock-names = "apb_pclk";
+ };
+
+ usb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x31020000 0x00001000>;
+
+ /*
+ * Enable either ohci or usbd (gadget)!
+ */
+ ohci: ohci@0 {
+ compatible = "nxp,ohci-nxp", "usb-ohci";
+ reg = <0x0 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
+ status = "disabled";
+ };
+
+ usbd: usbd@0 {
+ compatible = "nxp,lpc3220-udc";
+ reg = <0x0 0x300>;
+ interrupt-parent = <&sic1>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
+ <30 IRQ_TYPE_LEVEL_HIGH>,
+ <28 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
+ status = "disabled";
+ };
+
+ i2cusb: i2c@300 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x300 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usbclk: clock-controller@f00 {
+ compatible = "nxp,lpc3220-usb-clk";
+ reg = <0xf00 0x100>;
+ #clock-cells = <1>;
+ };
+ };
+
+ clcd: clcd@31040000 {
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x31040000 0x1000>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
+ clock-names = "clcdclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ mac: ethernet@31060000 {
+ compatible = "nxp,lpc-eth";
+ reg = <0x31060000 0x1000>;
+ interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_MAC>;
+ status = "disabled";
+ };
+
+ emc: memory-controller@31080000 {
+ compatible = "arm,pl175", "arm,primecell";
+ reg = <0x31080000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
+ clock-names = "mpmcclk", "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0xe0000000 0x01000000>,
+ <1 0xe1000000 0x01000000>,
+ <2 0xe2000000 0x01000000>,
+ <3 0xe3000000 0x01000000>;
+ status = "disabled";
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x20000000 0x20000000 0x30000000>;
+
+ /*
+ * ssp0 and spi1 are shared pins;
+ * enable one in your board dts, as needed.
+ */
+ ssp0: spi@20084000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x20084000 0x1000>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SSP0>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@20088000 {
+ compatible = "nxp,lpc3220-spi";
+ reg = <0x20088000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SPI1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /*
+ * ssp1 and spi2 are shared pins;
+ * enable one in your board dts, as needed.
+ */
+ ssp1: spi@2008c000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x2008c000 0x1000>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SSP1>;
+ clock-names = "apb_pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@20090000 {
+ compatible = "nxp,lpc3220-spi";
+ reg = <0x20090000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_SPI2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@20094000 {
+ compatible = "nxp,lpc3220-i2s";
+ reg = <0x20094000 0x1000>;
+ status = "disabled";
+ };
+
+ sd: sd@20098000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ reg = <0x20098000 0x1000>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
+ <13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_SD>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ i2s1: i2s@2009c000 {
+ compatible = "nxp,lpc3220-i2s";
+ reg = <0x2009c000 0x1000>;
+ status = "disabled";
+ };
+
+ /* UART5 first since it is the default console, ttyS0 */
+ uart5: serial@40090000 {
+ /* actually, ns16550a w/ 64 byte fifos! */
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40090000 0x1000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART5>;
+ status = "disabled";
+ };
+
+ uart3: serial@40080000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40080000 0x1000>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@40088000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40088000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART4>;
+ status = "disabled";
+ };
+
+ uart6: serial@40098000 {
+ compatible = "nxp,lpc3220-uart";
+ reg = <0x40098000 0x1000>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ clocks = <&clk LPC32XX_CLK_UART6>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@400a0000 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x400a0000 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk LPC32XX_CLK_I2C1>;
+ };
+
+ i2c2: i2c@400a8000 {
+ compatible = "nxp,pnx-i2c";
+ reg = <0x400a8000 0x100>;
+ interrupt-parent = <&sic1>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk LPC32XX_CLK_I2C2>;
+ };
+
+ mpwm: mpwm@400e8000 {
+ compatible = "nxp,lpc3220-motor-pwm";
+ reg = <0x400e8000 0x78>;
+ status = "disabled";
+ #pwm-cells = <2>;
+ };
+ };
+
+ fab {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x20000000 0x20000000 0x30000000>;
+
+ /* System Control Block */
+ scb {
+ compatible = "simple-bus";
+ ranges = <0x0 0x040004000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clk: clock-controller@0 {
+ compatible = "nxp,lpc3220-clk";
+ reg = <0x00 0x114>;
+ #clock-cells = <1>;
+
+ clocks = <&xtal_32k>, <&xtal>;
+ clock-names = "xtal_32k", "xtal";
+ };
+ };
+
+ mic: interrupt-controller@40008000 {
+ compatible = "nxp,lpc3220-mic";
+ reg = <0x40008000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sic1: interrupt-controller@4000c000 {
+ compatible = "nxp,lpc3220-sic";
+ reg = <0x4000c000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&mic>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
+ <30 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sic2: interrupt-controller@40010000 {
+ compatible = "nxp,lpc3220-sic";
+ reg = <0x40010000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&mic>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
+ <31 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ uart1: serial@40014000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x40014000 0x1000>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@40018000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x40018000 0x1000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart7: serial@4001c000 {
+ compatible = "nxp,lpc3220-hsuart";
+ reg = <0x4001c000 0x1000>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ rtc: rtc@40024000 {
+ compatible = "nxp,lpc3220-rtc";
+ reg = <0x40024000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_RTC>;
+ };
+
+ gpio: gpio@40028000 {
+ compatible = "nxp,lpc3220-gpio";
+ reg = <0x40028000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <3>; /* bank, pin, flags */
+ };
+
+ timer4: timer@4002c000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x4002c000 0x1000>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER4>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ timer5: timer@40030000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40030000 0x1000>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER5>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ watchdog: watchdog@4003c000 {
+ compatible = "nxp,pnx4008-wdt";
+ reg = <0x4003c000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_WDOG>;
+ };
+
+ timer0: timer@40044000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40044000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_TIMER0>;
+ clock-names = "timerclk";
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ /*
+ * TSC vs. ADC: Since those two share the same
+ * hardware, you need to choose from one of the
+ * following two and do 'status = "okay";' for one of
+ * them
+ */
+
+ adc: adc@40048000 {
+ compatible = "nxp,lpc3220-adc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_ADC>;
+ status = "disabled";
+ };
+
+ tsc: tsc@40048000 {
+ compatible = "nxp,lpc3220-tsc";
+ reg = <0x40048000 0x1000>;
+ interrupt-parent = <&sic1>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk LPC32XX_CLK_ADC>;
+ status = "disabled";
+ };
+
+ timer1: timer@4004c000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x4004c000 0x1000>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER1>;
+ clock-names = "timerclk";
+ };
+
+ key: key@40050000 {
+ compatible = "nxp,lpc3220-key";
+ reg = <0x40050000 0x1000>;
+ clocks = <&clk LPC32XX_CLK_KEY>;
+ interrupt-parent = <&sic1>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer2: timer@40058000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40058000 0x1000>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER2>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@4005c000 {
+ compatible = "nxp,lpc3220-pwm";
+ reg = <0x4005c000 0x4>;
+ clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@4005c004 {
+ compatible = "nxp,lpc3220-pwm";
+ reg = <0x4005c004 0x4>;
+ clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
+ assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
+ status = "disabled";
+ };
+
+ timer3: timer@40060000 {
+ compatible = "nxp,lpc3220-timer";
+ reg = <0x40060000 0x1000>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk LPC32XX_CLK_TIMER3>;
+ clock-names = "timerclk";
+ status = "disabled";
+ };
+ };
+ };
+};
diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h
new file mode 100644
index 0000000000..e624d3a527
--- /dev/null
+++ b/include/dt-bindings/clock/lpc32xx-clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This code is released using a dual license strategy: BSD/GPL
+ * You can choose the licence that better fits your requirements.
+ *
+ * Released under the terms of 3-clause BSD License
+ * Released under the terms of GNU General Public License Version 2.0
+ *
+ */
+
+#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H
+#define __DT_BINDINGS_LPC32XX_CLOCK_H
+
+/* LPC32XX System Control Block clocks */
+#define LPC32XX_CLK_RTC 1
+#define LPC32XX_CLK_DMA 2
+#define LPC32XX_CLK_MLC 3
+#define LPC32XX_CLK_SLC 4
+#define LPC32XX_CLK_LCD 5
+#define LPC32XX_CLK_MAC 6
+#define LPC32XX_CLK_SD 7
+#define LPC32XX_CLK_DDRAM 8
+#define LPC32XX_CLK_SSP0 9
+#define LPC32XX_CLK_SSP1 10
+#define LPC32XX_CLK_UART3 11
+#define LPC32XX_CLK_UART4 12
+#define LPC32XX_CLK_UART5 13
+#define LPC32XX_CLK_UART6 14
+#define LPC32XX_CLK_IRDA 15
+#define LPC32XX_CLK_I2C1 16
+#define LPC32XX_CLK_I2C2 17
+#define LPC32XX_CLK_TIMER0 18
+#define LPC32XX_CLK_TIMER1 19
+#define LPC32XX_CLK_TIMER2 20
+#define LPC32XX_CLK_TIMER3 21
+#define LPC32XX_CLK_TIMER4 22
+#define LPC32XX_CLK_TIMER5 23
+#define LPC32XX_CLK_WDOG 24
+#define LPC32XX_CLK_I2S0 25
+#define LPC32XX_CLK_I2S1 26
+#define LPC32XX_CLK_SPI1 27
+#define LPC32XX_CLK_SPI2 28
+#define LPC32XX_CLK_MCPWM 29
+#define LPC32XX_CLK_HSTIMER 30
+#define LPC32XX_CLK_KEY 31
+#define LPC32XX_CLK_PWM1 32
+#define LPC32XX_CLK_PWM2 33
+#define LPC32XX_CLK_ADC 34
+#define LPC32XX_CLK_HCLK_PLL 35
+#define LPC32XX_CLK_PERIPH 36
+
+/* LPC32XX USB clocks */
+#define LPC32XX_USB_CLK_I2C 1
+#define LPC32XX_USB_CLK_DEVICE 2
+#define LPC32XX_USB_CLK_HOST 3
+
+#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */
--
2.30.0.rc0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v1 3/3] arm: lpc32xx: add EA LPC3250 DevKitv2 board support
2021-06-07 4:33 [PATCH v1 0/3] lpc32xx updates Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 1/3] lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX Trevor Woerner
2021-06-07 4:33 ` [PATCH v1 2/3] lpc32xx: import device tree from Linux Trevor Woerner
@ 2021-06-07 4:33 ` Trevor Woerner
2 siblings, 0 replies; 4+ messages in thread
From: Trevor Woerner @ 2021-06-07 4:33 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Jagan Teki, Kever Yang, Andre Przywara, Fabio Estevam,
Patrick Delaunay, Tim Harvey, Peter Robinson, Heiko Schocher,
Heiko Stuebner, Lokesh Vutla
Add basic support for running U-Boot on the Embedded Artists LPC3250
Developer's Kit v2 board by launching U-Boot from the board's s1l loader
(which comes pre-installed on the board).
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/lpc3250-ea3250-u-boot.dtsi | 15 ++
arch/arm/mach-lpc32xx/Kconfig | 4 +
board/ea/ea-lpc3250devkitv2/Kconfig | 15 ++
board/ea/ea-lpc3250devkitv2/MAINTAINERS | 9 ++
board/ea/ea-lpc3250devkitv2/Makefile | 4 +
board/ea/ea-lpc3250devkitv2/README.rst | 132 ++++++++++++++++++
.../ea-lpc3250devkitv2/ea-lpc3250devkitv2.c | 37 +++++
configs/ea-lpc3250devkitv2_defconfig | 23 +++
include/configs/ea-lpc3250devkitv2.h | 37 +++++
10 files changed, 278 insertions(+)
create mode 100644 arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
create mode 100644 board/ea/ea-lpc3250devkitv2/Kconfig
create mode 100644 board/ea/ea-lpc3250devkitv2/MAINTAINERS
create mode 100644 board/ea/ea-lpc3250devkitv2/Makefile
create mode 100644 board/ea/ea-lpc3250devkitv2/README.rst
create mode 100644 board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
create mode 100644 configs/ea-lpc3250devkitv2_defconfig
create mode 100644 include/configs/ea-lpc3250devkitv2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..134108f14e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1103,6 +1103,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
new file mode 100644
index 0000000000..0c82e512c6
--- /dev/null
+++ b/arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+/{
+ model = "Embedded Artists LPC3250 DevKit v2 board based on the NXP LPC3250 SoC";
+ chosen {
+ stdout-path = &uart5;
+ };
+};
+
+&uart5 {
+ compatible = "nxp,lpc3220-uart", "ns16550a";
+};
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 986ad738ac..185bda41c2 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -12,9 +12,13 @@ config TARGET_DEVKIT3250
config TARGET_WORK_92105
bool "Work Microwave Work_92105"
+config TARGET_EA_LPC3250DEVKITV2
+ bool "Embedded Artists LPC3250 Developer's Kit v2"
+
endchoice
source "board/timll/devkit3250/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
+source "board/ea/ea-lpc3250devkitv2/Kconfig"
endif
diff --git a/board/ea/ea-lpc3250devkitv2/Kconfig b/board/ea/ea-lpc3250devkitv2/Kconfig
new file mode 100644
index 0000000000..368ce027e6
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EA_LPC3250DEVKITV2
+
+config SYS_BOARD
+ default "ea-lpc3250devkitv2"
+
+config SYS_VENDOR
+ default "ea"
+
+config SYS_SOC
+ default "lpc32xx"
+
+config SYS_CONFIG_NAME
+ default "ea-lpc3250devkitv2"
+
+endif
diff --git a/board/ea/ea-lpc3250devkitv2/MAINTAINERS b/board/ea/ea-lpc3250devkitv2/MAINTAINERS
new file mode 100644
index 0000000000..b4b9362f5b
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/MAINTAINERS
@@ -0,0 +1,9 @@
+EMBEDDED ARTISTS LPC3250 DEVKIT v2
+M: Trevor Woerner <twoerner@gmail.com>
+S: Maintained
+F: board/ea/ea-lpc3250devkitv2
+F: include/configs/ea-lpc3250devkitv2.h
+F: configs/ea-lpc3250devkitv2_defconfig
+F: arch/arm/dts/lpc32xx.dtsi
+F: arch/arm/dts/lpc3250-ea3250.dts
+F: arch/arm/dts/lpc3250-ea3250-u-boot.dtsi
diff --git a/board/ea/ea-lpc3250devkitv2/Makefile b/board/ea/ea-lpc3250devkitv2/Makefile
new file mode 100644
index 0000000000..a4a40b6d4f
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+
+obj-y += ea-lpc3250devkitv2.o
diff --git a/board/ea/ea-lpc3250devkitv2/README.rst b/board/ea/ea-lpc3250devkitv2/README.rst
new file mode 100644
index 0000000000..56b5d0dbb1
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/README.rst
@@ -0,0 +1,132 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+ToC:
+- Introduction
+- Booting
+- Debugging
+
+
+Introduction
+============
+The Embedded Artists LPC3250 Developer's Kit v2 features the LPC3250 SoC
+which is based on the ARM926EJ-S CPU. The kit features a base board and
+a removable OEM board which features the SoC. Details, schematics, and
+documentation are available from the Embedded Artists product website:
+
+ https://www.embeddedartists.com/products/lpc3250-developers-kit-v2/
+
+The base board includes::
+- 200 pos, 0.6mm pitch SODIMM connector for OEM Board
+- LCD expansion connector with control signals for touch screen interface
+- Expansion connector with all OEM Board signals
+- Ethernet connector (RJ45)
+- CAN interface & connector (provision for second CAN interface, but not mounted)
+- MMC/SD interface & connector
+- USB1: OTG or Host interface & connector
+- USB2: Device or Host interface & connector
+- Provision for NXP JN5148 RF module (former Jennic) interface (RF module not included)
+- Full modem RS232 (cannot be fully used on 32-bit databus OEM boards)
+- RS422/485 interface & connector
+- Provision for IrDA transceiver interface (transceiver not mounted)
+- I2S audio codec (mic in, line in, line out, headphone out)
+- SWD/JTAG connector
+- Trace connector and pads for ETM connector
+- Serial Expansion Connector, 14-pos connector with UART/I2C/SPI/GPIO pins
+- Power supply, either via USB or external 5V DC
+- Optional coin cell battery for RTC and LED on ALARM output (coin cell not included)
+- OEM Board current measuring
+- Parallel NOR flash on external memory bus
+- 16-bit register and LEDs on external memory bus
+- 5-key joystick
+- LM75 temperature sensor (I2C connected)
+- 5 push-button keys (four via I2C and one on ISP-ENABLE)
+- 9 LEDs (8 via I2C and one on ISP-ENABLE)
+- Trimming potentiometer to analog input
+- USB-to-serial bridge on UART #0 (FT232R) and ISP functionality
+- Reset push-button and LED
+- Speaker output on analog output from OEM Board, or from I2S audio codec
+- 160x150 mm in size
+
+The OEM board::
+- ARMv5 ARM926EJ-S @ 266 MHz with hard-float VFPv2
+- 256 KByte IRAM, 64 MByte SDRAM
+- 128 MByte NAND flash
+- 4 MByte NOR Flash
+- Graphics Output: Parallel RGB
+- Hardware 2D/3D Graphic: No
+- Hardware Video: SW only
+- Graphics input: No
+- Audio: I2S
+- Ethernet: 10/100 Mbps
+- USB: 1x FS USB 2.0 OTG
+- Wi-Fi: No
+- FlexIO: No
+- Serial: 2x I2C, 2x SPI, 7x UART
+- ADC/PWM: 3 ch (10-bit) / 2 ch
+- SD: MCI
+- PCIe: No
+- Serial ATA: No
+- Size: 68 x 48 mm
+- Connector: 200 pos SODIMM
+
+
+Booting
+=======
+The processor will start its code execution from an internal ROM,
+containing the boot code. This boot loader can load code from one of four
+external sources to internal RAM (IRAM) at address 0x0::
+- UART5
+- SSP0 (in SPI mode)
+- EMC Static CS0 memory
+- NAND FLASH
+
+The ROM boot loader loads code as a single contiguous block at a maximum
+size of 56 kByte. Programs larger than this size must be loaded in more
+steps, for example, by a secondary boot loader.
+
+Kickstart Loader
+----------------
+By default the Embedded Artists LPC3250 OEM Board is programmed with the
+kickstart loader in block 0 of the NAND flash. The responsibility of this
+loader is to load an application stored in block 1 and onwards of the NAND
+flash. The kickstart loader will load the application into internal RAM
+(IRAM) at address 0x0.
+
+Stage 1 Loader (s1l)
+--------------------
+By default the Embedded Artists LPC3250 OEM Board is programmed with the
+stage 1 loader (s1l) in block 1 of the NAND flash. This application will be
+loaded by the kickstart loader when the LPC3250 OEM Board powers up. The
+S1L loader will initialize the board, such as clocks and external memory
+and then start a console where you can give input commands to the loader.
+S1L offers the following booting options::
+- MMC/SD card
+- UART5
+- NAND Flash
+
+U-Boot with kickstart+s1l
+-------------------------
+Out of the box, the easiest way to get U-Boot running on the EA LPC3250
+DevKit v2 board is to build the ea-lpc3250devkitv2_defconfig, copy the
+resulting u-boot.bin to a vfat-formatted MMC/SD card, insert the MMC/SD card
+into the MMC/SD card slot on the board, reset the board (SW1), and::
+
+ Embedded Artist 3250 Board (S1L 2.0)
+ Build date: Oct 31 2016 13:00:37
+
+ EA3250>load blk u-boot.bin raw 0x83000000
+ File loaded successfully
+
+ EA3250>exec 0x83000000
+
+
+Debugging
+=========
+JTAG debugging of the Embedded Artists LPC3250 Developer's Kit v2 board is
+easy thanks to the included/populated 20-pin JTAG port on the main board (J8).
+openocd 0.11 has been used with this board along with the ARM-USB-OCD-H JTAG
+dongle from Olimex successfully as follows:
+
+ # openocd \
+ -f interface/ftdi/olimex-arm-usb-ocd-h.cfg \
+ -f board/phytec_lpc3250.cfg
diff --git a/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
new file mode 100644
index 0000000000..7a19400041
--- /dev/null
+++ b/board/ea/ea-lpc3250devkitv2/ea-lpc3250devkitv2.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+#include <init.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int
+board_early_init_f(void)
+{
+ lpc32xx_uart_init(CONFIG_CONS_INDEX);
+ return 0;
+}
+
+int
+board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x2000;
+ return 0;
+}
+
+int
+dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_64M);
+ return 0;
+}
diff --git a/configs/ea-lpc3250devkitv2_defconfig b/configs/ea-lpc3250devkitv2_defconfig
new file mode 100644
index 0000000000..dc90e16475
--- /dev/null
+++ b/configs/ea-lpc3250devkitv2_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_LPC32XX=y
+CONFIG_SYS_TEXT_BASE=0x83000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_EA_LPC3250DEVKITV2=y
+CONFIG_DEFAULT_DEVICE_TREE="lpc3250-ea3250"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+# CONFIG_AUTOBOOT is not set
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="EA-LPC3250v2=> "
+CONFIG_CMD_GPIO=y
+CONFIG_OF_CONTROL=y
+# CONFIG_NET is not set
+CONFIG_LPC32XX_GPIO=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_CONS_INDEX=5
+CONFIG_SYS_NS16550=y
+CONFIG_PANIC_HANG=y
diff --git a/include/configs/ea-lpc3250devkitv2.h b/include/configs/ea-lpc3250devkitv2.h
new file mode 100644
index 0000000000..c1a37c8a79
--- /dev/null
+++ b/include/configs/ea-lpc3250devkitv2.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Embedded Artists LPC3250 DevKit v2
+ * Copyright (C) 2021 Trevor Woerner <twoerner@gmail.com>
+ */
+
+#ifndef __CONFIG_EA_LPC3250DEVKITV2_H__
+#define __CONFIG_EA_LPC3250DEVKITV2_H__
+
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * SoC and board defines
+ */
+#define CONFIG_MACH_TYPE MACH_TYPE_LPC3XXX
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_SIZE_LIMIT 0x000fffff /* maximum allowable size for full U-Boot binary */
+
+/*
+ * RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
+
+/*
+ * cmd
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80100000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SoC-specific config
+ */
+#include <asm/arch/config.h>
+
+#endif
--
2.30.0.rc0
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