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From: Peter Zijlstra <peterz@infradead.org>
To: Leo Yan <leo.yan@linaro.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 03/11] coresight: tmc-etf: Add comment for store ordering
Date: Tue, 13 Jul 2021 14:56:06 +0200	[thread overview]
Message-ID: <20210713125606.GB4170@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20210711104105.505728-4-leo.yan@linaro.org>

On Sun, Jul 11, 2021 at 06:40:57PM +0800, Leo Yan wrote:
> AUX ring buffer is required to separate the data store and aux_head
> store, since the function CS_LOCK() has contained memory barrier mb(),
> mb() is a more conservative barrier than smp_wmb() on Arm32/Arm64, thus
> it's needless to add any explicit barrier anymore.
> 
> Add comment to make clear for the barrier usage for ETF.
> 
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 45b85edfc690..9a42ee689921 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -553,6 +553,12 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
>  	if (buf->snapshot)
>  		handle->head += to_read;
>  
> +	/*
> +	 * AUX ring buffer requires to use memory barrier to separate the trace
> +	 * data store and aux_head store, because CS_LOCK() contains mb() which
> +	 * gives more heavy barrier than smp_wmb(), it's not necessary to
> +	 * explicitly invoke any barrier.
> +	 */
>  	CS_LOCK(drvdata->base);

'more heavy' is not a correctness argument :-)

The argument to make here is that CS_LOCK() ensures completion /
visibility of the hardware buffer.

WARNING: multiple messages have this Message-ID (diff)
From: Peter Zijlstra <peterz@infradead.org>
To: Leo Yan <leo.yan@linaro.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 03/11] coresight: tmc-etf: Add comment for store ordering
Date: Tue, 13 Jul 2021 14:56:06 +0200	[thread overview]
Message-ID: <20210713125606.GB4170@worktop.programming.kicks-ass.net> (raw)
In-Reply-To: <20210711104105.505728-4-leo.yan@linaro.org>

On Sun, Jul 11, 2021 at 06:40:57PM +0800, Leo Yan wrote:
> AUX ring buffer is required to separate the data store and aux_head
> store, since the function CS_LOCK() has contained memory barrier mb(),
> mb() is a more conservative barrier than smp_wmb() on Arm32/Arm64, thus
> it's needless to add any explicit barrier anymore.
> 
> Add comment to make clear for the barrier usage for ETF.
> 
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
>  drivers/hwtracing/coresight/coresight-tmc-etf.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 45b85edfc690..9a42ee689921 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -553,6 +553,12 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
>  	if (buf->snapshot)
>  		handle->head += to_read;
>  
> +	/*
> +	 * AUX ring buffer requires to use memory barrier to separate the trace
> +	 * data store and aux_head store, because CS_LOCK() contains mb() which
> +	 * gives more heavy barrier than smp_wmb(), it's not necessary to
> +	 * explicitly invoke any barrier.
> +	 */
>  	CS_LOCK(drvdata->base);

'more heavy' is not a correctness argument :-)

The argument to make here is that CS_LOCK() ensures completion /
visibility of the hardware buffer.

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  reply	other threads:[~2021-07-13 12:57 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-11 10:40 [PATCH v4 00/11] perf: Refine barriers for AUX ring buffer Leo Yan
2021-07-11 10:40 ` Leo Yan
2021-07-11 10:40 ` [PATCH v4 01/11] perf/ring_buffer: Add comment for barriers on " Leo Yan
2021-07-11 10:40   ` Leo Yan
2021-07-11 10:40 ` [PATCH v4 02/11] coresight: tmc-etr: Add barrier after updating " Leo Yan
2021-07-11 10:40   ` Leo Yan
2021-07-12 10:40   ` Suzuki K Poulose
2021-07-12 10:40     ` Suzuki K Poulose
2021-07-12 10:54     ` Leo Yan
2021-07-12 10:54       ` Leo Yan
2021-07-11 10:40 ` [PATCH v4 03/11] coresight: tmc-etf: Add comment for store ordering Leo Yan
2021-07-11 10:40   ` Leo Yan
2021-07-13 12:56   ` Peter Zijlstra [this message]
2021-07-13 12:56     ` Peter Zijlstra
2021-07-13 15:49     ` Leo Yan
2021-07-13 15:49       ` Leo Yan
2021-07-11 10:40 ` [PATCH v4 04/11] perf/x86: Add barrier after updating bts Leo Yan
2021-07-11 10:40   ` Leo Yan
2021-07-13 13:01   ` Peter Zijlstra
2021-07-13 13:01     ` Peter Zijlstra
2021-07-11 10:40 ` [PATCH v4 05/11] perf auxtrace: Use WRITE_ONCE() for updating aux_tail Leo Yan
2021-07-11 10:40   ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 06/11] perf auxtrace: Drop legacy __sync functions Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 07/11] perf auxtrace: Remove auxtrace_mmap__read_snapshot_head() Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-12 14:32   ` Adrian Hunter
2021-07-12 14:32     ` Adrian Hunter
2021-07-13 13:10     ` Leo Yan
2021-07-13 13:10       ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 08/11] perf: Cleanup for HAVE_SYNC_COMPARE_AND_SWAP_SUPPORT Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 09/11] tools: Remove feature-sync-compare-and-swap feature detection Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 10/11] perf env: Set flag for kernel is 64-bit mode Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-12 14:37   ` Adrian Hunter
2021-07-12 14:37     ` Adrian Hunter
2021-07-12 18:14   ` Arnaldo Carvalho de Melo
2021-07-12 18:14     ` Arnaldo Carvalho de Melo
2021-07-13 15:09     ` Leo Yan
2021-07-13 15:09       ` Leo Yan
2021-07-13 17:31       ` Hunter, Adrian
2021-07-13 17:31         ` Hunter, Adrian
2021-07-14 13:59         ` Arnaldo Carvalho de Melo
2021-07-14 13:59           ` Arnaldo Carvalho de Melo
2021-07-14 14:00           ` Arnaldo Carvalho de Melo
2021-07-14 14:00             ` Arnaldo Carvalho de Melo
2021-07-23  7:11             ` Leo Yan
2021-07-23  7:11               ` Leo Yan
2021-07-11 10:41 ` [PATCH v4 11/11] perf auxtrace: Add compat_auxtrace_mmap__{read_head|write_tail} Leo Yan
2021-07-11 10:41   ` Leo Yan
2021-07-12 14:44   ` Russell King (Oracle)
2021-07-12 14:44     ` Russell King (Oracle)
2021-07-13 15:46     ` Leo Yan
2021-07-13 15:46       ` Leo Yan
2021-07-13 16:14       ` Russell King (Oracle)
2021-07-13 16:14         ` Russell King (Oracle)
2021-07-13 18:13         ` Catalin Marinas
2021-07-13 18:13           ` Catalin Marinas
2021-07-14  8:40           ` Russell King (Oracle)
2021-07-14  8:40             ` Russell King (Oracle)
2021-07-23  7:23             ` Leo Yan
2021-07-23  7:23               ` Leo Yan
2021-07-13  7:07   ` Adrian Hunter
2021-07-13  7:07     ` Adrian Hunter
2021-07-13 15:48     ` Leo Yan
2021-07-13 15:48       ` Leo Yan

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