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From: Catalin Marinas <catalin.marinas@arm.com>
To: Guangbin Huang <huangguangbin2@huawei.com>
Cc: davem@davemloft.net, kuba@kernel.org, will@kernel.org,
	maz@kernel.org, mark.rutland@arm.com, dbrazdil@google.com,
	qperret@google.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lipeng321@huawei.com
Subject: Re: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately
Date: Fri, 30 Jul 2021 10:42:22 +0100	[thread overview]
Message-ID: <20210730094222.GB8570@arm.com> (raw)
In-Reply-To: <1627614864-50824-3-git-send-email-huangguangbin2@huawei.com>

On Fri, Jul 30, 2021 at 11:14:22AM +0800, Guangbin Huang wrote:
> From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
> 
> Device registers can be mapped as write-combine type. In this case, data
> are not written into the device immediately. They are temporarily stored
> in the write combine buffer and written into the device when the buffer
> is full. But in some situation, we need to flush the write combine
> buffer to device immediately for better performance. So we add a general
> function called 'flush_wc_write()'. We use DGH instruction to implement
> this function for ARM64.

Isn't this slightly misleading? IIUC DGH does not guarantee flushing, it
just prevents writes merging (maybe this was already discussed on the
previous RFC).

-- 
Catalin

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WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Guangbin Huang <huangguangbin2@huawei.com>
Cc: davem@davemloft.net, kuba@kernel.org, will@kernel.org,
	maz@kernel.org, mark.rutland@arm.com, dbrazdil@google.com,
	qperret@google.com, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, lipeng321@huawei.com
Subject: Re: [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately
Date: Fri, 30 Jul 2021 10:42:22 +0100	[thread overview]
Message-ID: <20210730094222.GB8570@arm.com> (raw)
In-Reply-To: <1627614864-50824-3-git-send-email-huangguangbin2@huawei.com>

On Fri, Jul 30, 2021 at 11:14:22AM +0800, Guangbin Huang wrote:
> From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
> 
> Device registers can be mapped as write-combine type. In this case, data
> are not written into the device immediately. They are temporarily stored
> in the write combine buffer and written into the device when the buffer
> is full. But in some situation, we need to flush the write combine
> buffer to device immediately for better performance. So we add a general
> function called 'flush_wc_write()'. We use DGH instruction to implement
> this function for ARM64.

Isn't this slightly misleading? IIUC DGH does not guarantee flushing, it
just prevents writes merging (maybe this was already discussed on the
previous RFC).

-- 
Catalin

  parent reply	other threads:[~2021-07-30  9:44 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-30  3:14 [PATCH net-next 0/4] net: hns3: add support for TX push Guangbin Huang
2021-07-30  3:14 ` Guangbin Huang
2021-07-30  3:14 ` [PATCH net-next 1/4] arm64: barrier: add DGH macros to control memory accesses merging Guangbin Huang
2021-07-30  3:14   ` Guangbin Huang
2021-07-30  9:39   ` Catalin Marinas
2021-07-30  9:39     ` Catalin Marinas
2021-07-30  3:14 ` [PATCH net-next 2/4] io: add function to flush the write combine buffer to device immediately Guangbin Huang
2021-07-30  3:14   ` Guangbin Huang
2021-07-30  9:00   ` Will Deacon
2021-07-30  9:00     ` Will Deacon
2021-10-11 13:37     ` huangguangbin (A)
2021-10-11 13:37       ` huangguangbin (A)
2021-10-15  1:48     ` Xiongfeng Wang
2021-10-15  1:48       ` Xiongfeng Wang
2021-07-30  9:42   ` Catalin Marinas [this message]
2021-07-30  9:42     ` Catalin Marinas
2021-07-30  3:14 ` [PATCH net-next 3/4] net: hns3: add support for TX push mode Guangbin Huang
2021-07-30  3:14   ` Guangbin Huang
2021-07-30  3:14 ` [PATCH net-next 4/4] net: hns3: add ethtool priv-flag for TX push Guangbin Huang
2021-07-30  3:14   ` Guangbin Huang

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