All of lore.kernel.org
 help / color / mirror / Atom feed
From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
	maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com,
	heiko@sntech.de, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V5 2/3] dt-bindings: update riscv plic compatible string
Date: Sun, 24 Oct 2021 09:33:02 +0800	[thread overview]
Message-ID: <20211024013303.3499461-3-guoren@kernel.org> (raw)
In-Reply-To: <20211024013303.3499461-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>

---

Changes since V5:
 - Add DT list
 - Fixup compatible string
 - Remove allwinner-d1 compatible
 - make dt_binding_check

Changes since V4:
 - Update description in errata style
 - Update enum suggested by Anup, Heiko, Samuel

Changes since V3:
 - Rename "c9xx" to "c900"
 - Add thead,c900-plic in the description section
---
 .../interrupt-controller/sifive,plic-1.0.0.yaml   | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..18b97bfd7954 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic couldn't complete masked irq source which has been disabled in
+  enable register. Add thead_plic_chip which fix up c906-plic irq source completion
+  problem by unmask/mask wrapper.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,11 +46,16 @@ maintainers:
 
 properties:
   compatible:
-    items:
+   oneOf:
+    - items:
       - enum:
-          - sifive,fu540-c000-plic
-          - canaan,k210-plic
+        - sifive,fu540-c000-plic
+        - canaan,k210-plic
       - const: sifive,plic-1.0.0
+    - items:
+      - enum:
+        - allwinner,sun20i-d1-plic
+      - const: thead,c900-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
	maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com,
	heiko@sntech.de, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V5 2/3] dt-bindings: update riscv plic compatible string
Date: Sun, 24 Oct 2021 09:33:02 +0800	[thread overview]
Message-ID: <20211024013303.3499461-3-guoren@kernel.org> (raw)
In-Reply-To: <20211024013303.3499461-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>

---

Changes since V5:
 - Add DT list
 - Fixup compatible string
 - Remove allwinner-d1 compatible
 - make dt_binding_check

Changes since V4:
 - Update description in errata style
 - Update enum suggested by Anup, Heiko, Samuel

Changes since V3:
 - Rename "c9xx" to "c900"
 - Add thead,c900-plic in the description section
---
 .../interrupt-controller/sifive,plic-1.0.0.yaml   | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..18b97bfd7954 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic couldn't complete masked irq source which has been disabled in
+  enable register. Add thead_plic_chip which fix up c906-plic irq source completion
+  problem by unmask/mask wrapper.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,11 +46,16 @@ maintainers:
 
 properties:
   compatible:
-    items:
+   oneOf:
+    - items:
       - enum:
-          - sifive,fu540-c000-plic
-          - canaan,k210-plic
+        - sifive,fu540-c000-plic
+        - canaan,k210-plic
       - const: sifive,plic-1.0.0
+    - items:
+      - enum:
+        - allwinner,sun20i-d1-plic
+      - const: thead,c900-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


  parent reply	other threads:[~2021-10-24  1:33 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-24  1:33 [PATCH V5 0/3] Add thead,c900-plic support guoren
2021-10-24  1:33 ` guoren
2021-10-24  1:33 ` [PATCH V5 1/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-24  1:33   ` guoren
2021-11-02  2:21   ` Guo Ren
2021-11-02  2:21     ` Guo Ren
2021-11-02 12:59     ` Rob Herring
2021-11-02 12:59       ` Rob Herring
2021-11-03  1:52       ` Guo Ren
2021-11-03  1:52         ` Guo Ren
2021-10-24  1:33 ` guoren [this message]
2021-10-24  1:33   ` [PATCH V5 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-24  7:35   ` Anup Patel
2021-10-24  7:35     ` Anup Patel
2021-10-24  9:01     ` Guo Ren
2021-10-24  9:01       ` Guo Ren
2021-10-24  9:18       ` Anup Patel
2021-10-24  9:18         ` Anup Patel
2021-10-24  9:35         ` Guo Ren
2021-10-24  9:35           ` Guo Ren
2021-10-24  9:52           ` Anup Patel
2021-10-24  9:52             ` Anup Patel
2021-10-24 10:04             ` Guo Ren
2021-10-24 10:04               ` Guo Ren
2021-10-24  1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT guoren
2021-10-24  1:33   ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " guoren
2021-10-25 10:48   ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2021-10-25 10:48     ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2021-10-25 13:33     ` Guo Ren
2021-10-25 13:33       ` Guo Ren
2021-10-28 10:55     ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Nikita Shubin
2021-10-28 10:55       ` Nikita Shubin
2021-10-28 14:58       ` Marc Zyngier
2021-10-28 14:58         ` Marc Zyngier
2021-10-30 10:27         ` Anup Patel
2021-10-30 10:27           ` Anup Patel
2021-11-01  2:20         ` Guo Ren
2021-11-01  2:20           ` Guo Ren
2021-11-01  2:53           ` Anup Patel
2021-11-01  2:53             ` Anup Patel
2021-11-01  3:57             ` Guo Ren
2021-11-01  3:57               ` Guo Ren
2021-11-01  4:27               ` Anup Patel
2021-11-01  4:27                 ` Anup Patel
2021-11-01  7:56                 ` Guo Ren
2021-11-01  7:56                   ` Guo Ren
2021-11-01  9:27                 ` Marc Zyngier
2021-11-01  9:27                   ` Marc Zyngier
2021-11-01  9:25           ` Marc Zyngier
2021-11-01  9:25             ` Marc Zyngier
2021-11-01  2:00       ` Guo Ren
2021-11-01  2:00         ` Guo Ren
2021-11-01  5:11       ` Vincent Pelletier
2021-11-01  5:11         ` Vincent Pelletier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211024013303.3499461-3-guoren@kernel.org \
    --to=guoren@kernel.org \
    --cc=anup@brainfault.org \
    --cc=atish.patra@wdc.com \
    --cc=guoren@linux.alibaba.com \
    --cc=heiko@sntech.de \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=palmer@dabbelt.com \
    --cc=palmerdabbelt@google.com \
    --cc=robh+dt@kernel.org \
    --cc=robh@kernel.org \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.