From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: "Guo Ren" <guoren@kernel.org>,
"Nikita Shubin" <nikita.shubin@maquefel.me>,
"Atish Patra" <atish.patra@wdc.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Rob Herring" <robh@kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT
Date: Mon, 01 Nov 2021 09:27:39 +0000 [thread overview]
Message-ID: <87ee809qes.wl-maz@kernel.org> (raw)
In-Reply-To: <CAAhSdy3r2oVOq9yd+ZkOs1oCHRH-qvjLDa25Jp3qeD1tSxWEWQ@mail.gmail.com>
On Mon, 01 Nov 2021 04:27:50 +0000,
Anup Patel <anup@brainfault.org> wrote:
> The RISC-V AIA will totally replace RISC-V PLIC going forward. In fact,
> RISC-V AIA APLIC addresses all limitations of RISC-V PLIC along with
> new features additions.
Instead of arguing about yet another piece of RISC-V vapourware, how
about you guys propose a patch that would actually make the *current*
HW work to some extent?
M.
--
Without deviation from the norm, progress is not possible.
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http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <anup@brainfault.org>
Cc: "Guo Ren" <guoren@kernel.org>,
"Nikita Shubin" <nikita.shubin@maquefel.me>,
"Atish Patra" <atish.patra@wdc.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Heiko Stübner" <heiko@sntech.de>,
"Rob Herring" <robh@kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
"Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT
Date: Mon, 01 Nov 2021 09:27:39 +0000 [thread overview]
Message-ID: <87ee809qes.wl-maz@kernel.org> (raw)
In-Reply-To: <CAAhSdy3r2oVOq9yd+ZkOs1oCHRH-qvjLDa25Jp3qeD1tSxWEWQ@mail.gmail.com>
On Mon, 01 Nov 2021 04:27:50 +0000,
Anup Patel <anup@brainfault.org> wrote:
> The RISC-V AIA will totally replace RISC-V PLIC going forward. In fact,
> RISC-V AIA APLIC addresses all limitations of RISC-V PLIC along with
> new features additions.
Instead of arguing about yet another piece of RISC-V vapourware, how
about you guys propose a patch that would actually make the *current*
HW work to some extent?
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-11-01 9:27 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-24 1:33 [PATCH V5 0/3] Add thead,c900-plic support guoren
2021-10-24 1:33 ` guoren
2021-10-24 1:33 ` [PATCH V5 1/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-24 1:33 ` guoren
2021-11-02 2:21 ` Guo Ren
2021-11-02 2:21 ` Guo Ren
2021-11-02 12:59 ` Rob Herring
2021-11-02 12:59 ` Rob Herring
2021-11-03 1:52 ` Guo Ren
2021-11-03 1:52 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-24 1:33 ` guoren
2021-10-24 7:35 ` Anup Patel
2021-10-24 7:35 ` Anup Patel
2021-10-24 9:01 ` Guo Ren
2021-10-24 9:01 ` Guo Ren
2021-10-24 9:18 ` Anup Patel
2021-10-24 9:18 ` Anup Patel
2021-10-24 9:35 ` Guo Ren
2021-10-24 9:35 ` Guo Ren
2021-10-24 9:52 ` Anup Patel
2021-10-24 9:52 ` Anup Patel
2021-10-24 10:04 ` Guo Ren
2021-10-24 10:04 ` Guo Ren
2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT guoren
2021-10-24 1:33 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " guoren
2021-10-25 10:48 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2021-10-25 10:48 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2021-10-25 13:33 ` Guo Ren
2021-10-25 13:33 ` Guo Ren
2021-10-28 10:55 ` [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic " Nikita Shubin
2021-10-28 10:55 ` Nikita Shubin
2021-10-28 14:58 ` Marc Zyngier
2021-10-28 14:58 ` Marc Zyngier
2021-10-30 10:27 ` Anup Patel
2021-10-30 10:27 ` Anup Patel
2021-11-01 2:20 ` Guo Ren
2021-11-01 2:20 ` Guo Ren
2021-11-01 2:53 ` Anup Patel
2021-11-01 2:53 ` Anup Patel
2021-11-01 3:57 ` Guo Ren
2021-11-01 3:57 ` Guo Ren
2021-11-01 4:27 ` Anup Patel
2021-11-01 4:27 ` Anup Patel
2021-11-01 7:56 ` Guo Ren
2021-11-01 7:56 ` Guo Ren
2021-11-01 9:27 ` Marc Zyngier [this message]
2021-11-01 9:27 ` Marc Zyngier
2021-11-01 9:25 ` Marc Zyngier
2021-11-01 9:25 ` Marc Zyngier
2021-11-01 2:00 ` Guo Ren
2021-11-01 2:00 ` Guo Ren
2021-11-01 5:11 ` Vincent Pelletier
2021-11-01 5:11 ` Vincent Pelletier
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