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From: wefu@redhat.com
To: anup.patel@wdc.com, atish.patra@wdc.com,
	palmerdabbelt@google.com, guoren@kernel.org,
	christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu,
	hch@lst.de, liush@allwinnertech.com, wefu@redhat.com,
	lazyparser@gmail.com, drew@beagleboard.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
	heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
	guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org,
	maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com,
	andrea.mondelli@huawei.com, behrensj@mit.edu,
	xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
	allen.baum@esperantotech.com, jscheid@ventanamicro.com,
	rtrauben@gmail.com, Anup Patel <anup@brainfault.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt
Date: Mon, 25 Oct 2021 12:06:06 +0800	[thread overview]
Message-ID: <20211025040607.92786-2-wefu@redhat.com> (raw)
In-Reply-To: <20211025040607.92786-1-wefu@redhat.com>

From: Wei Fu <wefu@redhat.com>

Previous patch has added svpbmt in arch/riscv and changed the
DT mmu-type. Update dt-bindings related property here.

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e534f6a7cfa1..76f324d85e12 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -59,6 +59,11 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  mmu-supports-svpbmt:
+    description:
+      Describes the CPU's mmu-supports-svpbmt support
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture
-- 
2.25.4


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WARNING: multiple messages have this Message-ID (diff)
From: wefu@redhat.com
To: anup.patel@wdc.com, atish.patra@wdc.com,
	palmerdabbelt@google.com, guoren@kernel.org,
	christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu,
	hch@lst.de, liush@allwinnertech.com, wefu@redhat.com,
	lazyparser@gmail.com, drew@beagleboard.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
	heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
	guoren@linux.alibaba.com, arnd@arndb.de, wens@csie.org,
	maxime@cerno.tech, dlustig@nvidia.com, gfavor@ventanamicro.com,
	andrea.mondelli@huawei.com, behrensj@mit.edu,
	xinhaoqu@huawei.com, huffman@cadence.com, mick@ics.forth.gr,
	allen.baum@esperantotech.com, jscheid@ventanamicro.com,
	rtrauben@gmail.com, Anup Patel <anup@brainfault.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Rob Herring <robh+dt@kernel.org>
Subject: [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt
Date: Mon, 25 Oct 2021 12:06:06 +0800	[thread overview]
Message-ID: <20211025040607.92786-2-wefu@redhat.com> (raw)
In-Reply-To: <20211025040607.92786-1-wefu@redhat.com>

From: Wei Fu <wefu@redhat.com>

Previous patch has added svpbmt in arch/riscv and changed the
DT mmu-type. Update dt-bindings related property here.

Signed-off-by: Wei Fu <wefu@redhat.com>
Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
Cc: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Rob Herring <robh+dt@kernel.org>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index e534f6a7cfa1..76f324d85e12 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -59,6 +59,11 @@ properties:
       - riscv,sv48
       - riscv,none
 
+  mmu-supports-svpbmt:
+    description:
+      Describes the CPU's mmu-supports-svpbmt support
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+
   riscv,isa:
     description:
       Identifies the specific RISC-V instruction set architecture
-- 
2.25.4


  reply	other threads:[~2021-10-25  4:06 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25  4:06 [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu
2021-10-25  4:06 ` wefu
2021-10-25  4:06 ` wefu [this message]
2021-10-25  4:06   ` [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt wefu
2021-10-25  4:17   ` Anup Patel
2021-10-25  4:17     ` Anup Patel
2021-10-25  6:00     ` Guo Ren
2021-10-25  6:00       ` Guo Ren
2021-10-25  6:08       ` Anup Patel
2021-10-25  6:08         ` Anup Patel
2021-10-25 13:21         ` Philipp Tomsich
2021-10-25 13:21           ` Philipp Tomsich
2021-10-25  6:09   ` Guo Ren
2021-10-25  6:09     ` Guo Ren
2021-10-25  4:06 ` [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-10-25  4:06   ` wefu
2021-10-25  6:55   ` Christoph Hellwig
2021-10-25  6:55     ` Christoph Hellwig
2021-10-25 10:55     ` Wei Fu
2021-10-25 10:55       ` Wei Fu
2021-11-02  6:07       ` Christoph Hellwig
2021-11-02  6:07         ` Christoph Hellwig
2021-11-07  7:23         ` Wei Fu
2021-11-07  7:23           ` Wei Fu
2021-10-25 14:49     ` Wei Fu
2021-10-25 14:49       ` Wei Fu
2021-11-02  6:04       ` Christoph Hellwig
2021-11-02  6:04         ` Christoph Hellwig
2021-11-07  6:54         ` Wei Fu
2021-11-07  6:54           ` Wei Fu
2021-10-27  0:12 ` [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Palmer Dabbelt
2021-10-27  0:12   ` Palmer Dabbelt
2021-10-27  7:54   ` Heinrich Schuchardt
2021-10-27  7:54     ` Heinrich Schuchardt
2021-11-02  2:07   ` Guo Ren
2021-11-02  2:07     ` Guo Ren
2021-11-02  5:58     ` Christoph Hellwig
2021-11-02  5:58       ` Christoph Hellwig
2021-11-02  8:51       ` Guo Ren
2021-11-02  8:51         ` Guo Ren
2021-11-07  7:12         ` Wei Fu
2021-11-07  7:12           ` Wei Fu
2021-11-08  7:52           ` Christoph Hellwig
2021-11-08  7:52             ` Christoph Hellwig
2021-11-26 16:23             ` Wei Fu
2021-11-26 16:23               ` Wei Fu

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