From: Christoph Hellwig <hch@lst.de>
To: Wei Fu <wefu@redhat.com>
Cc: "Christoph Hellwig" <hch@infradead.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
guoren@kernel.org, christoph.muellner@vrull.eu,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>,
"Liu Shaohua" <liush@allwinnertech.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
guoren@linux.alibaba.com, "Arnd Bergmann" <arnd@arndb.de>,
"Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports
Date: Tue, 2 Nov 2021 07:07:34 +0100 [thread overview]
Message-ID: <20211102060734.GB27015@lst.de> (raw)
In-Reply-To: <CA+YCwKkX64A8p9vfLJHC3+LqOWyDg99eDBR0mjfB=H45BOyJLQ@mail.gmail.com>
On Mon, Oct 25, 2021 at 06:55:09PM +0800, Wei Fu wrote:
> How about this macro:
> #define _SVPBMT_PMA 0x0UL
> #define _SVPBMT_NC BIT(61)
> #define _SVPBMT_IO BIT(62)
> #define _SVPBMT_MASK GENMASK(62, 61)
Personally I find these macros highly confusing.
#define _SVPBMT_PMA 0UL
#define _SVPBMT_NC (1UL << 61)
#define _SVPBMT_IO (1UL << 62).
#define _SVPBMT_MASK (_SVPBMT_NC | _SVPBMT_IO)
is much eaier to follow. Note that we can probably just drop
_SVPBMT_PMA entirely to make this even more readable.
> > Also why not use the standard names for these _PAGE bits used by
> > most other architectures?
>
> Which names are you suggesting? Would you mind providing an example ?
> _PAGE_BIT_ for _PAGE_KERNEL_ ??
Use _PAGE_NOCACHE for _SVPBMT_NC, and _PAGE_IO for _SVPBMT_IO.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Wei Fu <wefu@redhat.com>
Cc: "Christoph Hellwig" <hch@infradead.org>,
"Anup Patel" <anup.patel@wdc.com>,
"Atish Patra" <atish.patra@wdc.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
guoren@kernel.org, christoph.muellner@vrull.eu,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Christoph Hellwig" <hch@lst.de>,
"Liu Shaohua" <liush@allwinnertech.com>,
"Wei Wu (吴伟)" <lazyparser@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
taiten.peng@canonical.com, aniket.ponkshe@canonical.com,
heinrich.schuchardt@canonical.com, gordan.markus@canonical.com,
guoren@linux.alibaba.com, "Arnd Bergmann" <arnd@arndb.de>,
"Chen-Yu Tsai" <wens@csie.org>,
"Maxime Ripard" <maxime@cerno.tech>,
"Daniel Lustig" <dlustig@nvidia.com>,
"Greg Favor" <gfavor@ventanamicro.com>,
"Andrea Mondelli" <andrea.mondelli@huawei.com>,
"Jonathan Behrens" <behrensj@mit.edu>,
Xinhaoqu <xinhaoqu@huawei.com>,
"Bill Huffman" <huffman@cadence.com>,
"Nick Kossifidis" <mick@ics.forth.gr>,
"Allen Baum" <allen.baum@esperantotech.com>,
"Josh Scheid" <jscheid@ventanamicro.com>,
"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports
Date: Tue, 2 Nov 2021 07:07:34 +0100 [thread overview]
Message-ID: <20211102060734.GB27015@lst.de> (raw)
In-Reply-To: <CA+YCwKkX64A8p9vfLJHC3+LqOWyDg99eDBR0mjfB=H45BOyJLQ@mail.gmail.com>
On Mon, Oct 25, 2021 at 06:55:09PM +0800, Wei Fu wrote:
> How about this macro:
> #define _SVPBMT_PMA 0x0UL
> #define _SVPBMT_NC BIT(61)
> #define _SVPBMT_IO BIT(62)
> #define _SVPBMT_MASK GENMASK(62, 61)
Personally I find these macros highly confusing.
#define _SVPBMT_PMA 0UL
#define _SVPBMT_NC (1UL << 61)
#define _SVPBMT_IO (1UL << 62).
#define _SVPBMT_MASK (_SVPBMT_NC | _SVPBMT_IO)
is much eaier to follow. Note that we can probably just drop
_SVPBMT_PMA entirely to make this even more readable.
> > Also why not use the standard names for these _PAGE bits used by
> > most other architectures?
>
> Which names are you suggesting? Would you mind providing an example ?
> _PAGE_BIT_ for _PAGE_KERNEL_ ??
Use _PAGE_NOCACHE for _SVPBMT_NC, and _PAGE_IO for _SVPBMT_IO.
next prev parent reply other threads:[~2021-11-02 6:07 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 4:06 [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports wefu
2021-10-25 4:06 ` wefu
2021-10-25 4:06 ` [RESEND PATCH V3 1/2] dt-bindings: riscv: add mmu-supports-svpbmt for Svpbmt wefu
2021-10-25 4:06 ` wefu
2021-10-25 4:17 ` Anup Patel
2021-10-25 4:17 ` Anup Patel
2021-10-25 6:00 ` Guo Ren
2021-10-25 6:00 ` Guo Ren
2021-10-25 6:08 ` Anup Patel
2021-10-25 6:08 ` Anup Patel
2021-10-25 13:21 ` Philipp Tomsich
2021-10-25 13:21 ` Philipp Tomsich
2021-10-25 6:09 ` Guo Ren
2021-10-25 6:09 ` Guo Ren
2021-10-25 4:06 ` [RESEND PATCH V3 2/2] riscv: add RISC-V Svpbmt extension supports wefu
2021-10-25 4:06 ` wefu
2021-10-25 6:55 ` Christoph Hellwig
2021-10-25 6:55 ` Christoph Hellwig
2021-10-25 10:55 ` Wei Fu
2021-10-25 10:55 ` Wei Fu
2021-11-02 6:07 ` Christoph Hellwig [this message]
2021-11-02 6:07 ` Christoph Hellwig
2021-11-07 7:23 ` Wei Fu
2021-11-07 7:23 ` Wei Fu
2021-10-25 14:49 ` Wei Fu
2021-10-25 14:49 ` Wei Fu
2021-11-02 6:04 ` Christoph Hellwig
2021-11-02 6:04 ` Christoph Hellwig
2021-11-07 6:54 ` Wei Fu
2021-11-07 6:54 ` Wei Fu
2021-10-27 0:12 ` [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports Palmer Dabbelt
2021-10-27 0:12 ` Palmer Dabbelt
2021-10-27 7:54 ` Heinrich Schuchardt
2021-10-27 7:54 ` Heinrich Schuchardt
2021-11-02 2:07 ` Guo Ren
2021-11-02 2:07 ` Guo Ren
2021-11-02 5:58 ` Christoph Hellwig
2021-11-02 5:58 ` Christoph Hellwig
2021-11-02 8:51 ` Guo Ren
2021-11-02 8:51 ` Guo Ren
2021-11-07 7:12 ` Wei Fu
2021-11-07 7:12 ` Wei Fu
2021-11-08 7:52 ` Christoph Hellwig
2021-11-08 7:52 ` Christoph Hellwig
2021-11-26 16:23 ` Wei Fu
2021-11-26 16:23 ` Wei Fu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211102060734.GB27015@lst.de \
--to=hch@lst.de \
--cc=allen.baum@esperantotech.com \
--cc=andrea.mondelli@huawei.com \
--cc=aniket.ponkshe@canonical.com \
--cc=anup.patel@wdc.com \
--cc=arnd@arndb.de \
--cc=atish.patra@wdc.com \
--cc=behrensj@mit.edu \
--cc=christoph.muellner@vrull.eu \
--cc=dlustig@nvidia.com \
--cc=drew@beagleboard.org \
--cc=gfavor@ventanamicro.com \
--cc=gordan.markus@canonical.com \
--cc=guoren@kernel.org \
--cc=guoren@linux.alibaba.com \
--cc=hch@infradead.org \
--cc=heinrich.schuchardt@canonical.com \
--cc=huffman@cadence.com \
--cc=jscheid@ventanamicro.com \
--cc=lazyparser@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=liush@allwinnertech.com \
--cc=maxime@cerno.tech \
--cc=mick@ics.forth.gr \
--cc=palmerdabbelt@google.com \
--cc=philipp.tomsich@vrull.eu \
--cc=rtrauben@gmail.com \
--cc=taiten.peng@canonical.com \
--cc=wefu@redhat.com \
--cc=wens@csie.org \
--cc=xinhaoqu@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.