From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Fri, 10 Dec 2021 14:12:36 +0530 [thread overview]
Message-ID: <20211210084236.GC1734@thinkpad> (raw)
In-Reply-To: <20211208171442.1327689-2-dmitry.baryshkov@linaro.org>
On Wed, Dec 08, 2021 at 08:14:33PM +0300, Dmitry Baryshkov wrote:
> Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
> to the one used on SM8250. Add the compatible for SM8450.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Note to self: This binding should be converted to YAML very soon.
Thanks,
Mani
> ---
> .../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index a0ae024c2d0c..73bc763c5009 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -15,6 +15,7 @@
> - "qcom,pcie-sc8180x" for sc8180x
> - "qcom,pcie-sdm845" for sdm845
> - "qcom,pcie-sm8250" for sm8250
> + - "qcom,pcie-sm8450" for sm8450
> - "qcom,pcie-ipq6018" for ipq6018
>
> - reg:
> @@ -169,6 +170,24 @@
> - "ddrss_sf_tbu" PCIe SF TBU clock
> - "pipe" PIPE clock
>
> +- clock-names:
> + Usage: required for sm8450
> + Value type: <stringlist>
> + Definition: Should contain the following entries
> + - "aux" Auxiliary clock
> + - "cfg" Configuration clock
> + - "bus_master" Master AXI clock
> + - "bus_slave" Slave AXI clock
> + - "slave_q2a" Slave Q2A clock
> + - "tbu" PCIe TBU clock
> + - "ddrss_sf_tbu" PCIe SF TBU clock
> + - "pipe" PIPE clock
> + - "pipe_mux" PIPE MUX
> + - "phy_pipe" PIPE output clock
> + - "ref" REFERENCE clock
> + - "aggre0" Aggre NoC PCIe0 AXI clock
> + - "aggre1" Aggre NoC PCIe1 AXI clock
> +
> - resets:
> Usage: required
> Value type: <prop-encoded-array>
> @@ -246,7 +265,7 @@
> - "ahb" AHB reset
>
> - reset-names:
> - Usage: required for sc8180x, sdm845 and sm8250
> + Usage: required for sc8180x, sdm845, sm8250 and sm8450
> Value type: <stringlist>
> Definition: Should contain the following entries
> - "pci" PCIe core reset
> --
> 2.33.0
>
WARNING: multiple messages have this Message-ID (diff)
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH v2 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Fri, 10 Dec 2021 14:12:36 +0530 [thread overview]
Message-ID: <20211210084236.GC1734@thinkpad> (raw)
In-Reply-To: <20211208171442.1327689-2-dmitry.baryshkov@linaro.org>
On Wed, Dec 08, 2021 at 08:14:33PM +0300, Dmitry Baryshkov wrote:
> Document the PCIe DT bindings for SM8450 SoC.The PCIe IP is similar
> to the one used on SM8250. Add the compatible for SM8450.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Note to self: This binding should be converted to YAML very soon.
Thanks,
Mani
> ---
> .../devicetree/bindings/pci/qcom,pcie.txt | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index a0ae024c2d0c..73bc763c5009 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -15,6 +15,7 @@
> - "qcom,pcie-sc8180x" for sc8180x
> - "qcom,pcie-sdm845" for sdm845
> - "qcom,pcie-sm8250" for sm8250
> + - "qcom,pcie-sm8450" for sm8450
> - "qcom,pcie-ipq6018" for ipq6018
>
> - reg:
> @@ -169,6 +170,24 @@
> - "ddrss_sf_tbu" PCIe SF TBU clock
> - "pipe" PIPE clock
>
> +- clock-names:
> + Usage: required for sm8450
> + Value type: <stringlist>
> + Definition: Should contain the following entries
> + - "aux" Auxiliary clock
> + - "cfg" Configuration clock
> + - "bus_master" Master AXI clock
> + - "bus_slave" Slave AXI clock
> + - "slave_q2a" Slave Q2A clock
> + - "tbu" PCIe TBU clock
> + - "ddrss_sf_tbu" PCIe SF TBU clock
> + - "pipe" PIPE clock
> + - "pipe_mux" PIPE MUX
> + - "phy_pipe" PIPE output clock
> + - "ref" REFERENCE clock
> + - "aggre0" Aggre NoC PCIe0 AXI clock
> + - "aggre1" Aggre NoC PCIe1 AXI clock
> +
> - resets:
> Usage: required
> Value type: <prop-encoded-array>
> @@ -246,7 +265,7 @@
> - "ahb" AHB reset
>
> - reset-names:
> - Usage: required for sc8180x, sdm845 and sm8250
> + Usage: required for sc8180x, sdm845, sm8250 and sm8450
> Value type: <stringlist>
> Definition: Should contain the following entries
> - "pci" PCIe core reset
> --
> 2.33.0
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
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next prev parent reply other threads:[~2021-12-10 8:42 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:14 [PATCH v2 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 8:42 ` Manivannan Sadhasivam [this message]
2021-12-10 8:42 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 02/10] dt-bindings: phy: qcom, qmp: " Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 04/10] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 11:15 ` Manivannan Sadhasivam
2021-12-10 11:15 ` Manivannan Sadhasivam
2021-12-11 1:56 ` Dmitry Baryshkov
2021-12-11 1:56 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 05/10] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 11:22 ` Manivannan Sadhasivam
2021-12-10 11:22 ` Manivannan Sadhasivam
2021-12-11 1:59 ` Dmitry Baryshkov
2021-12-11 1:59 ` Dmitry Baryshkov
2021-12-11 3:11 ` Manivannan Sadhasivam
2021-12-11 3:11 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 06/10] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 11:30 ` Manivannan Sadhasivam
2021-12-10 11:30 ` Manivannan Sadhasivam
2021-12-11 2:01 ` Dmitry Baryshkov
2021-12-11 2:01 ` Dmitry Baryshkov
2021-12-11 3:07 ` Manivannan Sadhasivam
2021-12-11 3:07 ` Manivannan Sadhasivam
2021-12-08 17:14 ` [PATCH v2 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 11:37 ` Manivannan Sadhasivam
2021-12-10 11:37 ` Manivannan Sadhasivam
2021-12-11 2:10 ` Dmitry Baryshkov
2021-12-11 2:10 ` Dmitry Baryshkov
2021-12-08 17:14 ` [PATCH v2 08/10] arm64: dts: qcom: sm8450: add PCIe0 RC device Dmitry Baryshkov
2021-12-08 17:14 ` Dmitry Baryshkov
2021-12-10 12:06 ` Manivannan Sadhasivam
2021-12-10 12:06 ` Manivannan Sadhasivam
2021-12-11 2:24 ` Dmitry Baryshkov
2021-12-11 2:24 ` Dmitry Baryshkov
2021-12-12 21:34 ` Rob Herring
2021-12-12 21:34 ` Rob Herring
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