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From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>, Bin Meng <bmeng.cn@gmail.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
Date: Tue, 18 Jan 2022 16:47:35 +0530	[thread overview]
Message-ID: <20220118111736.454150-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220118111736.454150-1-apatel@ventanamicro.com>

Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 hw/riscv/spike.c        | 4 ++--
 include/hw/riscv/boot.h | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 597df4c288..d059a67f9b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine)
      */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     }
 
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index baff11dd8a..d486392cd0 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -25,9 +25,7 @@
 #include "hw/riscv/riscv_hart.h"
 
 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
-#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
-#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
 
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Anup Patel <apatel@ventanamicro.com>,
	qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	qemu-devel@nongnu.org, Atish Patra <atishp@atishpatra.org>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names
Date: Tue, 18 Jan 2022 16:47:35 +0530	[thread overview]
Message-ID: <20220118111736.454150-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220118111736.454150-1-apatel@ventanamicro.com>

Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 hw/riscv/spike.c        | 4 ++--
 include/hw/riscv/boot.h | 2 --
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 597df4c288..d059a67f9b 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -260,11 +260,11 @@ static void spike_board_init(MachineState *machine)
      */
     if (riscv_is_32bit(&s->soc[0])) {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV32_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     } else {
         firmware_end_addr = riscv_find_and_load_firmware(machine,
-                                    RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
+                                    RISCV64_BIOS_BIN, memmap[SPIKE_DRAM].base,
                                     htif_symbol_callback);
     }
 
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index baff11dd8a..d486392cd0 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -25,9 +25,7 @@
 #include "hw/riscv/riscv_hart.h"
 
 #define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
-#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
 #define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
-#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
 
 bool riscv_is_32bit(RISCVHartArrayState *harts);
 
-- 
2.25.1



  parent reply	other threads:[~2022-01-18 11:18 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-18 11:17 [PATCH v2 0/3] Improve RISC-V spike machine bios support Anup Patel
2022-01-18 11:17 ` Anup Patel
2022-01-18 11:17 ` [PATCH v2 1/3] hw/riscv: spike: Allow using binary firmware as bios Anup Patel
2022-01-18 11:17   ` Anup Patel
2022-01-18 22:30   ` Alistair Francis
2022-01-18 22:30     ` Alistair Francis
2022-01-19  6:55   ` Bin Meng
2022-01-19  6:55     ` Bin Meng
2022-01-18 11:17 ` Anup Patel [this message]
2022-01-18 11:17   ` [PATCH v2 2/3] hw/riscv: Remove macros for ELF BIOS image names Anup Patel
2022-01-18 22:30   ` Alistair Francis
2022-01-18 22:30     ` Alistair Francis
2022-01-19  6:55   ` Bin Meng
2022-01-19  6:55     ` Bin Meng
2022-01-18 11:17 ` [PATCH v2 3/3] roms/opensbi: Remove ELF images Anup Patel
2022-01-18 11:17   ` Anup Patel
2022-01-18 22:33   ` Alistair Francis
2022-01-18 22:33     ` Alistair Francis
2022-01-19  6:56   ` Bin Meng
2022-01-19  6:56     ` Bin Meng
2022-01-20 10:38     ` Anup Patel
2022-01-20 10:38       ` Anup Patel

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