All of lore.kernel.org
 help / color / mirror / Atom feed
From: kernel test robot <lkp@intel.com>
To: kbuild-all@lists.01.org
Subject: [esmil:visionfive 75/80] drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'?
Date: Wed, 19 Jan 2022 14:27:34 +0800	[thread overview]
Message-ID: <202201191446.e8ud7CAP-lkp@intel.com> (raw)

[-- Attachment #1: Type: text/plain, Size: 6457 bytes --]

tree:   https://github.com/esmil/linux visionfive
head:   e46c3a7e373e6faa03399f1a41c29cf7546c37cb
commit: 37af0be028777ba2227a48b8d94ff92f52f7aba7 [75/80] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp(a)intel.com/config)
compiler: riscv32-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/esmil/linux/commit/37af0be028777ba2227a48b8d94ff92f52f7aba7
        git remote add esmil https://github.com/esmil/linux
        git fetch --no-tags esmil visionfive
        git checkout 37af0be028777ba2227a48b8d94ff92f52f7aba7
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_flush64_range':
>> drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
     157 |                 writeq(line, l2_base + SIFIVE_L2_FLUSH64);
         |                 ^~~~~~
         |                 writeb
   cc1: some warnings being treated as errors


vim +157 drivers/soc/sifive/sifive_l2_cache.c

a967a289f16969 arch/riscv/mm/sifive_l2_cache.c      Yash Shah          2019-05-06  125  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  126  #ifdef CONFIG_SIFIVE_L2_FLUSH
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  127  void sifive_l2_flush64_range(unsigned long start, unsigned long len)
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  128  {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  129  	unsigned long line;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  130  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  131  	if(!l2_base) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  132  		pr_warn("L2CACHE: base addr invalid, skipping flush\n");
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  133  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  134  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  135  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  136  	/* TODO: if (len == 0), skipping flush or going on? */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  137  	if(!len) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  138  		pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  139  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  140  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  141  
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  142  	len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  143  	start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  144  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  145  	/* make sure the address is in the range */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  146  	if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  147  	   (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  148  			     CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
36921b04361a57 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21  149  		WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  150  		     start, len);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  151  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  152  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  153  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  154  	mb();	/* sync */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  155  	for (line = start; line < start + len;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  156  	     line += SIFIVE_L2_FLUSH64_LINE_LEN) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08 @157  		writeq(line, l2_base + SIFIVE_L2_FLUSH64);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  158  		mb();
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  159  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  160  }
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  161  EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  162  #endif
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  163  

:::::: The code@line 157 was first introduced by commit
:::::: d21f24663c127ec288f925cd991a1d767e1dd609 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function

:::::: TO: Tom <support@vamrs.com>
:::::: CC: Emil Renner Berthing <kernel@esmil.dk>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

WARNING: multiple messages have this Message-ID (diff)
From: kernel test robot <lkp@intel.com>
To: Emil Renner Berthing <kernel@esmil.dk>
Cc: kbuild-all@lists.01.org, linux-kernel@vger.kernel.org
Subject: [esmil:visionfive 75/80] drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'?
Date: Wed, 19 Jan 2022 14:27:34 +0800	[thread overview]
Message-ID: <202201191446.e8ud7CAP-lkp@intel.com> (raw)

tree:   https://github.com/esmil/linux visionfive
head:   e46c3a7e373e6faa03399f1a41c29cf7546c37cb
commit: 37af0be028777ba2227a48b8d94ff92f52f7aba7 [75/80] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs
config: riscv-randconfig-r002-20220118 (https://download.01.org/0day-ci/archive/20220119/202201191446.e8ud7CAP-lkp@intel.com/config)
compiler: riscv32-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/esmil/linux/commit/37af0be028777ba2227a48b8d94ff92f52f7aba7
        git remote add esmil https://github.com/esmil/linux
        git fetch --no-tags esmil visionfive
        git checkout 37af0be028777ba2227a48b8d94ff92f52f7aba7
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=riscv SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/soc/sifive/sifive_l2_cache.c: In function 'sifive_l2_flush64_range':
>> drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? [-Werror=implicit-function-declaration]
     157 |                 writeq(line, l2_base + SIFIVE_L2_FLUSH64);
         |                 ^~~~~~
         |                 writeb
   cc1: some warnings being treated as errors


vim +157 drivers/soc/sifive/sifive_l2_cache.c

a967a289f16969 arch/riscv/mm/sifive_l2_cache.c      Yash Shah          2019-05-06  125  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  126  #ifdef CONFIG_SIFIVE_L2_FLUSH
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  127  void sifive_l2_flush64_range(unsigned long start, unsigned long len)
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  128  {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  129  	unsigned long line;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  130  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  131  	if(!l2_base) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  132  		pr_warn("L2CACHE: base addr invalid, skipping flush\n");
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  133  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  134  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  135  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  136  	/* TODO: if (len == 0), skipping flush or going on? */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  137  	if(!len) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  138  		pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  139  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  140  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  141  
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  142  	len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN);
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  143  	start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN);
09426958620627 drivers/soc/sifive/sifive_l2_cache.c Atish Patra        2021-06-12  144  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  145  	/* make sure the address is in the range */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  146  	if(start < CONFIG_SIFIVE_L2_FLUSH_START ||
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  147  	   (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START +
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  148  			     CONFIG_SIFIVE_L2_FLUSH_SIZE)) {
36921b04361a57 drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21  149  		WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n",
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  150  		     start, len);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  151  		return;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  152  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  153  
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  154  	mb();	/* sync */
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  155  	for (line = start; line < start + len;
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  156  	     line += SIFIVE_L2_FLUSH64_LINE_LEN) {
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08 @157  		writeq(line, l2_base + SIFIVE_L2_FLUSH64);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  158  		mb();
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  159  	}
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  160  }
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  161  EXPORT_SYMBOL_GPL(sifive_l2_flush64_range);
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  162  #endif
d21f24663c127e drivers/soc/sifive/sifive_l2_cache.c Tom                2021-01-08  163  

:::::: The code at line 157 was first introduced by commit
:::::: d21f24663c127ec288f925cd991a1d767e1dd609 sifive/sifive_l2_cache: Add sifive_l2_flush64_range function

:::::: TO: Tom <support@vamrs.com>
:::::: CC: Emil Renner Berthing <kernel@esmil.dk>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

             reply	other threads:[~2022-01-19  6:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-19  6:27 kernel test robot [this message]
2022-01-19  6:27 ` [esmil:visionfive 75/80] drivers/soc/sifive/sifive_l2_cache.c:157:17: error: implicit declaration of function 'writeq'; did you mean 'writeb'? kernel test robot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=202201191446.e8ud7CAP-lkp@intel.com \
    --to=lkp@intel.com \
    --cc=kbuild-all@lists.01.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.