From: Ard Biesheuvel <ardb@kernel.org>
To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org
Cc: linux-hardening@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Nicolas Pitre <nico@fluxnic.net>, Arnd Bergmann <arnd@arndb.de>,
Kees Cook <keescook@chromium.org>,
Keith Packard <keithpac@amazon.com>,
Linus Walleij <linus.walleij@linaro.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tony Lindgren <tony@atomide.com>, Marc Zyngier <maz@kernel.org>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Jesse Taube <mr.bossman075@gmail.com>
Subject: [PATCH v5 03/32] ARM: footbridge: use GENERIC_IRQ_MULTI_HANDLER
Date: Mon, 24 Jan 2022 18:47:15 +0100 [thread overview]
Message-ID: <20220124174744.1054712-4-ardb@kernel.org> (raw)
In-Reply-To: <20220124174744.1054712-1-ardb@kernel.org>
From: Arnd Bergmann <arnd@arndb.de>
Footbridge still uses the classic IRQ entry path in assembler,
but this is easily converted into an equivalent C version.
In this case, the correlation between IRQ numbers and bits in
the status register is non-obvious, and the priorities are
handled by manually checking each bit in a static order,
re-reading the status register after each handled event.
I moved the code into the new file and edited the syntax without
changing this sequence to keep the behavior as close as possible
to what it traditionally did.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 1 +
| 87 ++++++++++++++++
| 107 --------------------
3 files changed, 88 insertions(+), 107 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40193ec76f1a..bef5085f2ce7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -361,6 +361,7 @@ config ARCH_FOOTBRIDGE
select FOOTBRIDGE
select NEED_MACH_IO_H if !MMU
select NEED_MACH_MEMORY_H
+ select GENERIC_IRQ_MULTI_HANDLER
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
--git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index eee095f0e2f6..322495df271d 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -27,6 +27,91 @@
#include "common.h"
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/hardware/dec21285.h>
+
+static int dc21285_get_irq(void)
+{
+ void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS;
+ u32 mask = readl(irqstatus);
+
+ if (mask & IRQ_MASK_SDRAMPARITY)
+ return IRQ_SDRAMPARITY;
+
+ if (mask & IRQ_MASK_UART_RX)
+ return IRQ_CONRX;
+
+ if (mask & IRQ_MASK_DMA1)
+ return IRQ_DMA1;
+
+ if (mask & IRQ_MASK_DMA2)
+ return IRQ_DMA2;
+
+ if (mask & IRQ_MASK_IN0)
+ return IRQ_IN0;
+
+ if (mask & IRQ_MASK_IN1)
+ return IRQ_IN1;
+
+ if (mask & IRQ_MASK_IN2)
+ return IRQ_IN2;
+
+ if (mask & IRQ_MASK_IN3)
+ return IRQ_IN3;
+
+ if (mask & IRQ_MASK_PCI)
+ return IRQ_PCI;
+
+ if (mask & IRQ_MASK_DOORBELLHOST)
+ return IRQ_DOORBELLHOST;
+
+ if (mask & IRQ_MASK_I2OINPOST)
+ return IRQ_I2OINPOST;
+
+ if (mask & IRQ_MASK_TIMER1)
+ return IRQ_TIMER1;
+
+ if (mask & IRQ_MASK_TIMER2)
+ return IRQ_TIMER2;
+
+ if (mask & IRQ_MASK_TIMER3)
+ return IRQ_TIMER3;
+
+ if (mask & IRQ_MASK_UART_TX)
+ return IRQ_CONTX;
+
+ if (mask & IRQ_MASK_PCI_ABORT)
+ return IRQ_PCI_ABORT;
+
+ if (mask & IRQ_MASK_PCI_SERR)
+ return IRQ_PCI_SERR;
+
+ if (mask & IRQ_MASK_DISCARD_TIMER)
+ return IRQ_DISCARD_TIMER;
+
+ if (mask & IRQ_MASK_PCI_DPERR)
+ return IRQ_PCI_DPERR;
+
+ if (mask & IRQ_MASK_PCI_PERR)
+ return IRQ_PCI_PERR;
+
+ return 0;
+}
+
+static void dc21285_handle_irq(struct pt_regs *regs)
+{
+ int irq;
+ do {
+ irq = dc21285_get_irq();
+ if (!irq)
+ break;
+
+ generic_handle_irq(irq);
+ } while (1);
+}
+
+
unsigned int mem_fclk_21285 = 50000000;
EXPORT_SYMBOL(mem_fclk_21285);
@@ -108,6 +193,8 @@ static void __init __fb_init_irq(void)
void __init footbridge_init_irq(void)
{
+ set_handle_irq(dc21285_handle_irq);
+
__fb_init_irq();
if (!footbridge_cfn_mode())
diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S
deleted file mode 100644
index dabbd5c54a78..000000000000
--- a/arch/arm/mach-footbridge/include/mach/entry-macro.S
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * arch/arm/mach-footbridge/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for footbridge-based platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <asm/hardware/dec21285.h>
-
- .equ dc21285_high, ARMCSR_BASE & 0xff000000
- .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
-
- .macro get_irqnr_preamble, base, tmp
- mov \base, #dc21285_high
- .if dc21285_low
- orr \base, \base, #dc21285_low
- .endif
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #0x180] @ get interrupts
-
- mov \irqnr, #IRQ_SDRAMPARITY
- tst \irqstat, #IRQ_MASK_SDRAMPARITY
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_UART_RX
- movne \irqnr, #IRQ_CONRX
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DMA1
- movne \irqnr, #IRQ_DMA1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DMA2
- movne \irqnr, #IRQ_DMA2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN0
- movne \irqnr, #IRQ_IN0
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN1
- movne \irqnr, #IRQ_IN1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN2
- movne \irqnr, #IRQ_IN2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN3
- movne \irqnr, #IRQ_IN3
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI
- movne \irqnr, #IRQ_PCI
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DOORBELLHOST
- movne \irqnr, #IRQ_DOORBELLHOST
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_I2OINPOST
- movne \irqnr, #IRQ_I2OINPOST
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER1
- movne \irqnr, #IRQ_TIMER1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER2
- movne \irqnr, #IRQ_TIMER2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER3
- movne \irqnr, #IRQ_TIMER3
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_UART_TX
- movne \irqnr, #IRQ_CONTX
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_ABORT
- movne \irqnr, #IRQ_PCI_ABORT
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_SERR
- movne \irqnr, #IRQ_PCI_SERR
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DISCARD_TIMER
- movne \irqnr, #IRQ_DISCARD_TIMER
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_DPERR
- movne \irqnr, #IRQ_PCI_DPERR
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_PERR
- movne \irqnr, #IRQ_PCI_PERR
-1001:
- .endm
-
--
2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Ard Biesheuvel <ardb@kernel.org>
To: linux@armlinux.org.uk, linux-arm-kernel@lists.infradead.org
Cc: linux-hardening@vger.kernel.org, Ard Biesheuvel <ardb@kernel.org>,
Nicolas Pitre <nico@fluxnic.net>, Arnd Bergmann <arnd@arndb.de>,
Kees Cook <keescook@chromium.org>,
Keith Packard <keithpac@amazon.com>,
Linus Walleij <linus.walleij@linaro.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tony Lindgren <tony@atomide.com>, Marc Zyngier <maz@kernel.org>,
Vladimir Murzin <vladimir.murzin@arm.com>,
Jesse Taube <mr.bossman075@gmail.com>
Subject: [PATCH v5 03/32] ARM: footbridge: use GENERIC_IRQ_MULTI_HANDLER
Date: Mon, 24 Jan 2022 18:47:15 +0100 [thread overview]
Message-ID: <20220124174744.1054712-4-ardb@kernel.org> (raw)
In-Reply-To: <20220124174744.1054712-1-ardb@kernel.org>
From: Arnd Bergmann <arnd@arndb.de>
Footbridge still uses the classic IRQ entry path in assembler,
but this is easily converted into an equivalent C version.
In this case, the correlation between IRQ numbers and bits in
the status register is non-obvious, and the priorities are
handled by manually checking each bit in a static order,
re-reading the status register after each handled event.
I moved the code into the new file and edited the syntax without
changing this sequence to keep the behavior as close as possible
to what it traditionally did.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com> # ARMv7M
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 1 +
| 87 ++++++++++++++++
| 107 --------------------
3 files changed, 88 insertions(+), 107 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40193ec76f1a..bef5085f2ce7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -361,6 +361,7 @@ config ARCH_FOOTBRIDGE
select FOOTBRIDGE
select NEED_MACH_IO_H if !MMU
select NEED_MACH_MEMORY_H
+ select GENERIC_IRQ_MULTI_HANDLER
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
--git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index eee095f0e2f6..322495df271d 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -27,6 +27,91 @@
#include "common.h"
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/hardware/dec21285.h>
+
+static int dc21285_get_irq(void)
+{
+ void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS;
+ u32 mask = readl(irqstatus);
+
+ if (mask & IRQ_MASK_SDRAMPARITY)
+ return IRQ_SDRAMPARITY;
+
+ if (mask & IRQ_MASK_UART_RX)
+ return IRQ_CONRX;
+
+ if (mask & IRQ_MASK_DMA1)
+ return IRQ_DMA1;
+
+ if (mask & IRQ_MASK_DMA2)
+ return IRQ_DMA2;
+
+ if (mask & IRQ_MASK_IN0)
+ return IRQ_IN0;
+
+ if (mask & IRQ_MASK_IN1)
+ return IRQ_IN1;
+
+ if (mask & IRQ_MASK_IN2)
+ return IRQ_IN2;
+
+ if (mask & IRQ_MASK_IN3)
+ return IRQ_IN3;
+
+ if (mask & IRQ_MASK_PCI)
+ return IRQ_PCI;
+
+ if (mask & IRQ_MASK_DOORBELLHOST)
+ return IRQ_DOORBELLHOST;
+
+ if (mask & IRQ_MASK_I2OINPOST)
+ return IRQ_I2OINPOST;
+
+ if (mask & IRQ_MASK_TIMER1)
+ return IRQ_TIMER1;
+
+ if (mask & IRQ_MASK_TIMER2)
+ return IRQ_TIMER2;
+
+ if (mask & IRQ_MASK_TIMER3)
+ return IRQ_TIMER3;
+
+ if (mask & IRQ_MASK_UART_TX)
+ return IRQ_CONTX;
+
+ if (mask & IRQ_MASK_PCI_ABORT)
+ return IRQ_PCI_ABORT;
+
+ if (mask & IRQ_MASK_PCI_SERR)
+ return IRQ_PCI_SERR;
+
+ if (mask & IRQ_MASK_DISCARD_TIMER)
+ return IRQ_DISCARD_TIMER;
+
+ if (mask & IRQ_MASK_PCI_DPERR)
+ return IRQ_PCI_DPERR;
+
+ if (mask & IRQ_MASK_PCI_PERR)
+ return IRQ_PCI_PERR;
+
+ return 0;
+}
+
+static void dc21285_handle_irq(struct pt_regs *regs)
+{
+ int irq;
+ do {
+ irq = dc21285_get_irq();
+ if (!irq)
+ break;
+
+ generic_handle_irq(irq);
+ } while (1);
+}
+
+
unsigned int mem_fclk_21285 = 50000000;
EXPORT_SYMBOL(mem_fclk_21285);
@@ -108,6 +193,8 @@ static void __init __fb_init_irq(void)
void __init footbridge_init_irq(void)
{
+ set_handle_irq(dc21285_handle_irq);
+
__fb_init_irq();
if (!footbridge_cfn_mode())
diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S
deleted file mode 100644
index dabbd5c54a78..000000000000
--- a/arch/arm/mach-footbridge/include/mach/entry-macro.S
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * arch/arm/mach-footbridge/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for footbridge-based platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <asm/hardware/dec21285.h>
-
- .equ dc21285_high, ARMCSR_BASE & 0xff000000
- .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
-
- .macro get_irqnr_preamble, base, tmp
- mov \base, #dc21285_high
- .if dc21285_low
- orr \base, \base, #dc21285_low
- .endif
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #0x180] @ get interrupts
-
- mov \irqnr, #IRQ_SDRAMPARITY
- tst \irqstat, #IRQ_MASK_SDRAMPARITY
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_UART_RX
- movne \irqnr, #IRQ_CONRX
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DMA1
- movne \irqnr, #IRQ_DMA1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DMA2
- movne \irqnr, #IRQ_DMA2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN0
- movne \irqnr, #IRQ_IN0
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN1
- movne \irqnr, #IRQ_IN1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN2
- movne \irqnr, #IRQ_IN2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_IN3
- movne \irqnr, #IRQ_IN3
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI
- movne \irqnr, #IRQ_PCI
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DOORBELLHOST
- movne \irqnr, #IRQ_DOORBELLHOST
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_I2OINPOST
- movne \irqnr, #IRQ_I2OINPOST
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER1
- movne \irqnr, #IRQ_TIMER1
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER2
- movne \irqnr, #IRQ_TIMER2
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_TIMER3
- movne \irqnr, #IRQ_TIMER3
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_UART_TX
- movne \irqnr, #IRQ_CONTX
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_ABORT
- movne \irqnr, #IRQ_PCI_ABORT
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_SERR
- movne \irqnr, #IRQ_PCI_SERR
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_DISCARD_TIMER
- movne \irqnr, #IRQ_DISCARD_TIMER
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_DPERR
- movne \irqnr, #IRQ_PCI_DPERR
- bne 1001f
-
- tst \irqstat, #IRQ_MASK_PCI_PERR
- movne \irqnr, #IRQ_PCI_PERR
-1001:
- .endm
-
--
2.30.2
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next prev parent reply other threads:[~2022-01-24 17:48 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 17:47 [PATCH v5 00/32] ARM vmap'ed and IRQ stacks roundup Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 01/32] ARM: riscpc: drop support for IOMD_IRQREQC/IOMD_IRQREQD IRQ groups Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 02/32] ARM: riscpc: use GENERIC_IRQ_MULTI_HANDLER Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel [this message]
2022-01-24 17:47 ` [PATCH v5 03/32] ARM: footbridge: " Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 04/32] ARM: iop32x: offset IRQ numbers by 1 Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 05/32] ARM: iop32x: use GENERIC_IRQ_MULTI_HANDLER Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 06/32] ARM: remove old-style irq entry Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 07/32] irqchip: nvic: Use GENERIC_IRQ_MULTI_HANDLER Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 08/32] ARM: decompressor: disable stack protector Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 09/32] ARM: stackprotector: prefer compiler for TLS based per-task protector Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 10/32] ARM: entry: preserve thread_info pointer in switch_to Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 11/32] ARM: module: implement support for PC-relative group relocations Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 12/32] ARM: assembler: add optimized ldr/str macros to load variables from memory Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 13/32] ARM: percpu: add SMP_ON_UP support Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 14/32] ARM: use TLS register for 'current' on !SMP as well Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 15/32] ARM: smp: defer TPIDRURO update for SMP v6 configurations too Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 16/32] ARM: implement THREAD_INFO_IN_TASK for uniprocessor systems Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 17/32] ARM: assembler: introduce bl_r macro Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 18/32] ARM: unwind: support unwinding across multiple stacks Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 19/32] ARM: export dump_mem() to other objects Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 20/32] ARM: unwind: dump exception stack from calling frame Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 21/32] ARM: backtrace-clang: avoid crash on bogus frame pointer Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 22/32] ARM: implement IRQ stacks Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 23/32] ARM: call_with_stack: add unwind support Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 24/32] ARM: run softirqs on the per-CPU IRQ stack Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-03-22 9:04 ` Sebastian Andrzej Siewior
2022-03-22 9:04 ` Sebastian Andrzej Siewior
2022-03-22 9:35 ` Ard Biesheuvel
2022-03-22 9:35 ` Ard Biesheuvel
2022-03-22 11:29 ` Sebastian Andrzej Siewior
2022-03-22 11:29 ` Sebastian Andrzej Siewior
2022-01-24 17:47 ` [PATCH v5 25/32] ARM: memcpy: use frame pointer as unwind anchor Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 26/32] ARM: memmove: " Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 27/32] ARM: memset: clean up unwind annotations Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 28/32] ARM: unwind: disregard unwind info before stack frame is set up Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 29/32] ARM: entry: rework stack realignment code in svc_entry Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 30/32] ARM: switch_to: clean up Thumb2 code path Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 31/32] ARM: mm: prepare vmalloc_seq handling for use under SMP Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:47 ` [PATCH v5 32/32] ARM: implement support for vmap'ed stacks Ard Biesheuvel
2022-01-24 17:47 ` Ard Biesheuvel
2022-01-24 17:56 ` [PATCH v5 00/32] ARM vmap'ed and IRQ stacks roundup Russell King (Oracle)
2022-01-24 17:56 ` Russell King (Oracle)
2022-01-24 17:57 ` Ard Biesheuvel
2022-01-24 17:57 ` Ard Biesheuvel
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