From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, maz@kernel.org,
tglx@linutronix.de, palmer@dabbelt.com, samuel@sholland.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH V6 0/2] Add thead,c900-plic support
Date: Sun, 30 Jan 2022 00:27:24 +0800 [thread overview]
Message-ID: <20220129162726.1154501-1-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.
Changes since V6:
- Modify sifive,plic-1.0.0.yaml comment
- Remove vendor-prefixes patch which has been merged
- Only put dt naming distinguish in sifive-plic.c
Changes since V5:
- Move back to mask/unmask
- Fixup the problem in eoi callback
- Remove allwinner,sun20i-d1 IRQCHIP_DECLARE
- Rewrite comment log
- Add DT list
- Fixup compatible string
- Remove allwinner-d1 compatible
- make dt_binding_check
- Add T-head vendor-prefixes
Changes since V4:
- Update description in errata style
- Update enum suggested by Anup, Heiko, Samuel
- Update comment by Anup
- Add cover-letter
Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
- Add sifive_plic_chip and thead_plic_chip for difference
Changes since V2:
- Add a separate compatible string "thead,c9xx-plic"
- set irq_mask/unmask of "plic_chip" to NULL and point
irq_enable/disable of "plic_chip" to plic_irq_mask/unmask
- Add a detailed comment block in plic_init() about the
differences in Claim/Completion process of RISC-V PLIC and C9xx
PLIC.
Guo Ren (2):
dt-bindings: update riscv plic compatible string
irqchip/sifive-plic: Fixup thead,c900-plic dt parse in opensbi
.../sifive,plic-1.0.0.yaml | 21 +++++++++++-----
drivers/irqchip/irq-sifive-plic.c | 25 +++++++++++++++++--
2 files changed, 38 insertions(+), 8 deletions(-)
--
2.25.1
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WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, maz@kernel.org,
tglx@linutronix.de, palmer@dabbelt.com, samuel@sholland.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH V6 0/2] Add thead,c900-plic support
Date: Sun, 30 Jan 2022 00:27:24 +0800 [thread overview]
Message-ID: <20220129162726.1154501-1-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.
Changes since V6:
- Modify sifive,plic-1.0.0.yaml comment
- Remove vendor-prefixes patch which has been merged
- Only put dt naming distinguish in sifive-plic.c
Changes since V5:
- Move back to mask/unmask
- Fixup the problem in eoi callback
- Remove allwinner,sun20i-d1 IRQCHIP_DECLARE
- Rewrite comment log
- Add DT list
- Fixup compatible string
- Remove allwinner-d1 compatible
- make dt_binding_check
- Add T-head vendor-prefixes
Changes since V4:
- Update description in errata style
- Update enum suggested by Anup, Heiko, Samuel
- Update comment by Anup
- Add cover-letter
Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
- Add sifive_plic_chip and thead_plic_chip for difference
Changes since V2:
- Add a separate compatible string "thead,c9xx-plic"
- set irq_mask/unmask of "plic_chip" to NULL and point
irq_enable/disable of "plic_chip" to plic_irq_mask/unmask
- Add a detailed comment block in plic_init() about the
differences in Claim/Completion process of RISC-V PLIC and C9xx
PLIC.
Guo Ren (2):
dt-bindings: update riscv plic compatible string
irqchip/sifive-plic: Fixup thead,c900-plic dt parse in opensbi
.../sifive,plic-1.0.0.yaml | 21 +++++++++++-----
drivers/irqchip/irq-sifive-plic.c | 25 +++++++++++++++++--
2 files changed, 38 insertions(+), 8 deletions(-)
--
2.25.1
next reply other threads:[~2022-01-29 16:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-29 16:27 guoren [this message]
2022-01-29 16:27 ` [PATCH V6 0/2] Add thead,c900-plic support guoren
2022-01-29 16:27 ` [PATCH V6 1/2] dt-bindings: update riscv plic compatible string guoren
2022-01-29 16:27 ` guoren
2022-01-29 16:27 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic dt parse in opensbi guoren
2022-01-29 16:27 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " guoren
2022-01-29 18:32 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-29 18:32 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30 2:08 ` Guo Ren
2022-01-30 2:08 ` Guo Ren
2022-01-30 2:50 ` Samuel Holland
2022-01-30 2:50 ` Samuel Holland
2022-01-30 4:39 ` Guo Ren
2022-01-30 4:39 ` Guo Ren
2022-01-30 10:28 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-30 10:28 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30 13:09 ` Guo Ren
2022-01-30 13:09 ` Guo Ren
2022-01-30 14:59 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-30 14:59 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30 15:11 ` Guo Ren
2022-01-30 15:11 ` Guo Ren
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