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From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, maz@kernel.org,
	tglx@linutronix.de, palmer@dabbelt.com, samuel@sholland.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>,
	Heiko Stuebner <heiko@sntech.de>, Rob Herring <robh@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V6 1/2] dt-bindings: update riscv plic compatible string
Date: Sun, 30 Jan 2022 00:27:25 +0800	[thread overview]
Message-ID: <20220129162726.1154501-2-guoren@kernel.org> (raw)
In-Reply-To: <20220129162726.1154501-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Samuel Holland <samuel@sholland.org>
---
 .../sifive,plic-1.0.0.yaml                    | 21 +++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 28b6b17fe4b2..1fa5aa7e4c2e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
+  T-HEAD PLIC implementation requires setting a delegation bit to allow access
+  from S-mode. So add thead,c900-plic to distinguish them.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,12 +46,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,fu540-c000-plic
-          - starfive,jh7100-plic
-          - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu540-c000-plic
+              - starfive,jh7100-plic
+              - canaan,k210-plic
+          - const: sifive,plic-1.0.0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-plic
+          - const: thead,c900-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


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WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, maz@kernel.org,
	tglx@linutronix.de, palmer@dabbelt.com, samuel@sholland.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	devicetree@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>,
	Heiko Stuebner <heiko@sntech.de>, Rob Herring <robh@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V6 1/2] dt-bindings: update riscv plic compatible string
Date: Sun, 30 Jan 2022 00:27:25 +0800	[thread overview]
Message-ID: <20220129162726.1154501-2-guoren@kernel.org> (raw)
In-Reply-To: <20220129162726.1154501-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Samuel Holland <samuel@sholland.org>
---
 .../sifive,plic-1.0.0.yaml                    | 21 +++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 28b6b17fe4b2..1fa5aa7e4c2e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,10 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
+  T-HEAD PLIC implementation requires setting a delegation bit to allow access
+  from S-mode. So add thead,c900-plic to distinguish them.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -42,12 +46,17 @@ maintainers:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - sifive,fu540-c000-plic
-          - starfive,jh7100-plic
-          - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+    oneOf:
+      - items:
+          - enum:
+              - sifive,fu540-c000-plic
+              - starfive,jh7100-plic
+              - canaan,k210-plic
+          - const: sifive,plic-1.0.0
+      - items:
+          - enum:
+              - allwinner,sun20i-d1-plic
+          - const: thead,c900-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


  reply	other threads:[~2022-01-29 16:28 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-29 16:27 [PATCH V6 0/2] Add thead,c900-plic support guoren
2022-01-29 16:27 ` guoren
2022-01-29 16:27 ` guoren [this message]
2022-01-29 16:27   ` [PATCH V6 1/2] dt-bindings: update riscv plic compatible string guoren
2022-01-29 16:27 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic dt parse in opensbi guoren
2022-01-29 16:27   ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " guoren
2022-01-29 18:32   ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-29 18:32     ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30  2:08     ` Guo Ren
2022-01-30  2:08       ` Guo Ren
2022-01-30  2:50       ` Samuel Holland
2022-01-30  2:50         ` Samuel Holland
2022-01-30  4:39         ` Guo Ren
2022-01-30  4:39           ` Guo Ren
2022-01-30 10:28           ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-30 10:28             ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30 13:09             ` Guo Ren
2022-01-30 13:09               ` Guo Ren
2022-01-30 14:59               ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead, c900-plic " Marc Zyngier
2022-01-30 14:59                 ` [PATCH V6 2/2] irqchip/sifive-plic: Fixup thead,c900-plic " Marc Zyngier
2022-01-30 15:11                 ` Guo Ren
2022-01-30 15:11                   ` Guo Ren

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