From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v6 2/6] drm/i915/gt: Drop invalidate_csb_entries
Date: Mon, 7 Feb 2022 12:11:23 -0800 [thread overview]
Message-ID: <20220207201127.648624-3-michael.cheng@intel.com> (raw)
In-Reply-To: <20220207201127.648624-1-michael.cheng@intel.com>
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..28f2581d3046 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size * sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
balasubramani.vivekanandan@intel.com, wayne.boyer@intel.com,
casey.g.bowman@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [PATCH v6 2/6] drm/i915/gt: Drop invalidate_csb_entries
Date: Mon, 7 Feb 2022 12:11:23 -0800 [thread overview]
Message-ID: <20220207201127.648624-3-michael.cheng@intel.com> (raw)
In-Reply-To: <20220207201127.648624-1-michael.cheng@intel.com>
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..28f2581d3046 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size * sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
next prev parent reply other threads:[~2022-02-07 20:11 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 20:11 [Intel-gfx] [PATCH v6 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 1/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` Michael Cheng [this message]
2022-02-07 20:11 ` [PATCH v6 2/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 3/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 4/6] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-09 16:52 ` [Intel-gfx] [PATCH] drm/i915/: fix noderef.cocci warnings kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-09 16:52 ` [Intel-gfx] [PATCH v6 4/6] drm/i915/: Re-work clflush_write32 kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 5/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 6/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-08 3:51 ` [Intel-gfx] " kernel test robot
2022-02-08 3:51 ` kernel test robot
2022-02-08 3:51 ` kernel test robot
2022-02-08 4:22 ` kernel test robot
2022-02-08 4:22 ` kernel test robot
2022-02-08 10:20 ` Tvrtko Ursulin
2022-02-08 10:20 ` Tvrtko Ursulin
2022-02-08 15:50 ` [Intel-gfx] " Michael Cheng
2022-02-08 15:50 ` Michael Cheng
2022-02-07 20:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev5) Patchwork
2022-02-07 20:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-07 21:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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