From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: michael.cheng@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v6 4/6] drm/i915/: Re-work clflush_write32
Date: Mon, 7 Feb 2022 12:11:25 -0800 [thread overview]
Message-ID: <20220207201127.648624-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220207201127.648624-1-michael.cheng@intel.com>
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
balasubramani.vivekanandan@intel.com, wayne.boyer@intel.com,
casey.g.bowman@intel.com, lucas.demarchi@intel.com,
dri-devel@lists.freedesktop.org
Subject: [PATCH v6 4/6] drm/i915/: Re-work clflush_write32
Date: Mon, 7 Feb 2022 12:11:25 -0800 [thread overview]
Message-ID: <20220207201127.648624-5-michael.cheng@intel.com> (raw)
In-Reply-To: <20220207201127.648624-1-michael.cheng@intel.com>
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
next prev parent reply other threads:[~2022-02-07 20:11 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-07 20:11 [Intel-gfx] [PATCH v6 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 1/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 2/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 3/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` Michael Cheng [this message]
2022-02-07 20:11 ` [PATCH v6 4/6] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-09 16:52 ` [Intel-gfx] [PATCH] drm/i915/: fix noderef.cocci warnings kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-09 16:52 ` [Intel-gfx] [PATCH v6 4/6] drm/i915/: Re-work clflush_write32 kernel test robot
2022-02-09 16:52 ` kernel test robot
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 5/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-07 20:11 ` [Intel-gfx] [PATCH v6 6/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-07 20:11 ` Michael Cheng
2022-02-08 3:51 ` [Intel-gfx] " kernel test robot
2022-02-08 3:51 ` kernel test robot
2022-02-08 3:51 ` kernel test robot
2022-02-08 4:22 ` kernel test robot
2022-02-08 4:22 ` kernel test robot
2022-02-08 10:20 ` Tvrtko Ursulin
2022-02-08 10:20 ` Tvrtko Ursulin
2022-02-08 15:50 ` [Intel-gfx] " Michael Cheng
2022-02-08 15:50 ` Michael Cheng
2022-02-07 20:29 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev5) Patchwork
2022-02-07 20:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-07 21:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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