* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices
2022-02-12 8:41 ` [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices Maciej W. Rozycki
2022-02-12 14:36 ` Andy Shevchenko
@ 2022-02-17 9:23 ` Dan Carpenter
0 siblings, 0 replies; 17+ messages in thread
From: kernel test robot @ 2022-02-12 18:17 UTC (permalink / raw)
To: kbuild
[-- Attachment #1: Type: text/plain, Size: 15364 bytes --]
CC: kbuild-all(a)lists.01.org
In-Reply-To: <alpine.DEB.2.21.2202111127200.34636@angie.orcam.me.uk>
References: <alpine.DEB.2.21.2202111127200.34636@angie.orcam.me.uk>
TO: "Maciej W. Rozycki" <macro@orcam.me.uk>
TO: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>
TO: Jiri Slaby <jirislaby@kernel.org>
CC: Andy Shevchenko <andy.shevchenko@gmail.com>
CC: Mike Skoog <mskoog@endruntechnologies.com>
CC: Mike Korreng <mkorreng@endruntechnologies.com>
CC: info(a)endruntechnologies.com
CC: linux-serial(a)vger.kernel.org
CC: linux-kernel(a)vger.kernel.org
Hi "Maciej,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on usb/usb-testing helgaas-pci/next linus/master v5.17-rc3 next-20220211]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
:::::: branch date: 7 hours ago
:::::: commit date: 7 hours ago
config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp(a)intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
New smatch warnings:
drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'.
drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'.
drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'.
Old smatch warnings:
drivers/tty/serial/8250/8250_pci.c:1176 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'.
drivers/tty/serial/8250/8250_pci.c:1190 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'.
vim +/tcr +1171 drivers/tty/serial/8250/8250_pci.c
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1049
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1050 /*
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1051 * Determine the oversampling rate, the clock prescaler, and the clock
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1052 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1053 * which is four times the baud base, and the prescaler increments in
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1054 * steps of 1/8. Therefore to make calculations on integers we need
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1055 * to use a scaled clock rate, which is the baud base multiplied by 32
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1056 * (or our assumed UART clock rate multiplied by 2).
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1057 *
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1058 * The allowed oversampling rates are from 4 up to 16 inclusive (values
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1059 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1060 * values between 1.000 and 63.875 inclusive (operation for values from
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1061 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1062 * unsigned 16-bit integer.
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1063 *
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1064 * For the most accurate baud rate we use a table of predetermined
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1065 * oversampling rates and clock prescalers that records all possible
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1066 * products of the two parameters in the range from 4 up to 255 inclusive,
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1067 * and additionally 335 for the 1500000bps rate, with the prescaler scaled
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1068 * by 8. The table is sorted by the decreasing value of the oversampling
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1069 * rate and ties are resolved by sorting by the decreasing value of the
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1070 * product. This way preference is given to higher oversampling rates.
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1071 *
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1072 * We iterate over the table and choose the product of an oversampling
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1073 * rate and a clock prescaler that gives the lowest integer division
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1074 * result deviation, or if an exact integer divider is found we stop
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1075 * looking for it right away. We do some fixup if the resulting clock
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1076 * divisor required would be out of its unsigned 16-bit integer range.
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1077 *
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1078 * Finally we abuse the supposed fractional part returned to encode the
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1079 * 4-bit value of the oversampling rate and the 9-bit value of the clock
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1080 * prescaler which will end up in the TCR and CPR/CPR2 registers.
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1081 */
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1082 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1083 unsigned int baud,
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1084 unsigned int *frac)
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1085 {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1086 static u8 p[][2] = {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1087 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1088 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1089 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1090 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1091 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1092 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1093 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1094 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1095 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1096 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1097 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1098 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1099 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1100 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1101 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1102 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1103 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1104 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1105 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1106 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1107 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1108 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1109 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1110 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1111 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1112 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1113 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1114 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1115 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1116 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1117 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1118 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1119 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1120 { 4, 9, }, { 4, 8, },
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1121 };
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1122 /* Scale the quotient for comparison to get the fractional part. */
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1123 const unsigned int quot_scale = 65536;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1124 unsigned int sclk = port->uartclk * 2;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1125 unsigned int sdiv = (sclk + (baud / 2)) / baud;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1126 unsigned int best_squot;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1127 unsigned int squot;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1128 unsigned int quot;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1129 u16 cpr;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1130 u8 tcr;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1131 int i;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1132
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1133 /* Old custom speed handling. */
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1134 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1135 unsigned int cust_div = port->custom_divisor;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1136
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1137 quot = cust_div & UART_DIV_MAX;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1138 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1139 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1140 if (cpr < OXSEMI_TORNADO_CPR_MIN)
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1141 cpr = OXSEMI_TORNADO_CPR_DEF;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1142 } else {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1143 best_squot = quot_scale;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1144 for (i = 0; i < ARRAY_SIZE(p); i++) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1145 unsigned int spre;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1146 unsigned int srem;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1147 u8 cp;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1148 u8 tc;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1149
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1150 tc = p[i][0];
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1151 cp = p[i][1];
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1152 spre = tc * cp;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1153
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1154 srem = sdiv % spre;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1155 if (srem > spre / 2)
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1156 srem = spre - srem;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1157 squot = (srem * quot_scale + spre / 2) / spre;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1158
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1159 if (srem == 0) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1160 tcr = tc;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1161 cpr = cp;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1162 quot = sdiv / spre;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1163 break;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1164 } else if (squot < best_squot) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1165 best_squot = squot;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1166 tcr = tc;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1167 cpr = cp;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1168 quot = (sdiv + spre / 2) / spre;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1169 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1170 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1171 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 &&
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1172 quot % 2 == 0) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1173 quot >>= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1174 tcr <<= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1175 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1176 while (quot > UART_DIV_MAX) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1177 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1178 quot >>= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1179 tcr <<= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1180 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1181 quot >>= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1182 cpr <<= 1;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1183 } else {
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1184 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1185 cpr = OXSEMI_TORNADO_CPR_MASK;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1186 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1187 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1188 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1189
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1190 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK);
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1191 return quot;
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1192 }
5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1193
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-17 9:23 ` Dan Carpenter 0 siblings, 0 replies; 17+ messages in thread From: Dan Carpenter @ 2022-02-17 9:23 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 6491 bytes --] Hi "Maciej, url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp(a)intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> New smatch warnings: drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. vim +/tcr +1171 drivers/tty/serial/8250/8250_pci.c 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1122 /* Scale the quotient for comparison to get the fractional part. */ 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1123 const unsigned int quot_scale = 65536; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1124 unsigned int sclk = port->uartclk * 2; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1125 unsigned int sdiv = (sclk + (baud / 2)) / baud; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1126 unsigned int best_squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1127 unsigned int squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1128 unsigned int quot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1129 u16 cpr; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1130 u8 tcr; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1131 int i; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1132 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1133 /* Old custom speed handling. */ 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1134 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1135 unsigned int cust_div = port->custom_divisor; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1136 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1137 quot = cust_div & UART_DIV_MAX; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1138 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1139 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1140 if (cpr < OXSEMI_TORNADO_CPR_MIN) 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1141 cpr = OXSEMI_TORNADO_CPR_DEF; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1142 } else { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1143 best_squot = quot_scale; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1144 for (i = 0; i < ARRAY_SIZE(p); i++) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1145 unsigned int spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1146 unsigned int srem; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1147 u8 cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1148 u8 tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1149 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1150 tc = p[i][0]; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1151 cp = p[i][1]; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1152 spre = tc * cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1153 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1154 srem = sdiv % spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1155 if (srem > spre / 2) 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1156 srem = spre - srem; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1157 squot = (srem * quot_scale + spre / 2) / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1158 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1159 if (srem == 0) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1160 tcr = tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1161 cpr = cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1162 quot = sdiv / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1163 break; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1164 } else if (squot < best_squot) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1165 best_squot = squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1166 tcr = tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1167 cpr = cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1168 quot = (sdiv + spre / 2) / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1169 } No else path. 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1170 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1171 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1172 quot % 2 == 0) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1173 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1174 tcr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1175 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1176 while (quot > UART_DIV_MAX) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1177 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1178 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1179 tcr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1180 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1181 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1182 cpr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1183 } else { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1184 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1185 cpr = OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1186 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1187 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1188 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1189 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1190 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1191 return quot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1192 } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-17 9:23 ` Dan Carpenter 0 siblings, 0 replies; 17+ messages in thread From: Dan Carpenter @ 2022-02-17 9:23 UTC (permalink / raw) To: kbuild, Maciej W. Rozycki, Greg Kroah-Hartman, Jiri Slaby Cc: lkp, kbuild-all, Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial, linux-kernel Hi "Maciej, url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp@intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> New smatch warnings: drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. vim +/tcr +1171 drivers/tty/serial/8250/8250_pci.c 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1122 /* Scale the quotient for comparison to get the fractional part. */ 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1123 const unsigned int quot_scale = 65536; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1124 unsigned int sclk = port->uartclk * 2; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1125 unsigned int sdiv = (sclk + (baud / 2)) / baud; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1126 unsigned int best_squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1127 unsigned int squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1128 unsigned int quot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1129 u16 cpr; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1130 u8 tcr; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1131 int i; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1132 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1133 /* Old custom speed handling. */ 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1134 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1135 unsigned int cust_div = port->custom_divisor; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1136 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1137 quot = cust_div & UART_DIV_MAX; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1138 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1139 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1140 if (cpr < OXSEMI_TORNADO_CPR_MIN) 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1141 cpr = OXSEMI_TORNADO_CPR_DEF; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1142 } else { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1143 best_squot = quot_scale; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1144 for (i = 0; i < ARRAY_SIZE(p); i++) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1145 unsigned int spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1146 unsigned int srem; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1147 u8 cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1148 u8 tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1149 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1150 tc = p[i][0]; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1151 cp = p[i][1]; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1152 spre = tc * cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1153 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1154 srem = sdiv % spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1155 if (srem > spre / 2) 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1156 srem = spre - srem; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1157 squot = (srem * quot_scale + spre / 2) / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1158 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1159 if (srem == 0) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1160 tcr = tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1161 cpr = cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1162 quot = sdiv / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1163 break; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1164 } else if (squot < best_squot) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1165 best_squot = squot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1166 tcr = tc; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1167 cpr = cp; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1168 quot = (sdiv + spre / 2) / spre; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1169 } No else path. 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1170 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1171 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1172 quot % 2 == 0) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1173 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1174 tcr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1175 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1176 while (quot > UART_DIV_MAX) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1177 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1178 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1179 tcr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 @1180 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1181 quot >>= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1182 cpr <<= 1; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1183 } else { 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1184 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1185 cpr = OXSEMI_TORNADO_CPR_MASK; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1186 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1187 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1188 } 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1189 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1190 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1191 return quot; 5a389fe2b5e750 Maciej W. Rozycki 2022-02-12 1192 } --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices 2022-02-17 9:23 ` Dan Carpenter @ 2022-02-17 12:05 ` Maciej W. Rozycki -1 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-17 12:05 UTC (permalink / raw) To: Dan Carpenter, Greg Kroah-Hartman Cc: kbuild, Jiri Slaby, lkp, kbuild-all, Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial, linux-kernel On Thu, 17 Feb 2022, Dan Carpenter wrote: > url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 > base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing > config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp@intel.com/config) > compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > New smatch warnings: > drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. > drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. > drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. These variables do get assigned to in the first iteration of the loop, because the deviation calculated (`srem') is normalised to the range of [0,spre/2] and that divided by the original divisor (`spre') always works out at within [0,0.5], so `squot' will be within [0,32768]. I guess the static analyser is too dumb to figure it out, so I'll see how to paper it over unless someone has a better proposal. Greg: shall I send an update patch or a replacement v4 of the series? Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-17 12:05 ` Maciej W. Rozycki 0 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-17 12:05 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 1485 bytes --] On Thu, 17 Feb 2022, Dan Carpenter wrote: > url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 > base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing > config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp(a)intel.com/config) > compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 > > If you fix the issue, kindly add following tag as appropriate > Reported-by: kernel test robot <lkp@intel.com> > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > New smatch warnings: > drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. > drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. > drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. These variables do get assigned to in the first iteration of the loop, because the deviation calculated (`srem') is normalised to the range of [0,spre/2] and that divided by the original divisor (`spre') always works out at within [0,0.5], so `squot' will be within [0,32768]. I guess the static analyser is too dumb to figure it out, so I'll see how to paper it over unless someone has a better proposal. Greg: shall I send an update patch or a replacement v4 of the series? Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices 2022-02-17 12:05 ` Maciej W. Rozycki (?) @ 2022-02-17 13:23 ` Dan Carpenter -1 siblings, 0 replies; 17+ messages in thread From: Dan Carpenter @ 2022-02-17 13:23 UTC (permalink / raw) To: Maciej W. Rozycki Cc: Greg Kroah-Hartman, kbuild, Jiri Slaby, lkp, kbuild-all, Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial, linux-kernel On Thu, Feb 17, 2022 at 12:05:58PM +0000, Maciej W. Rozycki wrote: > On Thu, 17 Feb 2022, Dan Carpenter wrote: > > > url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 > > base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing > > config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp@intel.com/config ) > > compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 > > > > If you fix the issue, kindly add following tag as appropriate > > Reported-by: kernel test robot <lkp@intel.com> > > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > > > New smatch warnings: > > drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. > > drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. > > drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. > > These variables do get assigned to in the first iteration of the loop, > because the deviation calculated (`srem') is normalised to the range of > [0,spre/2] and that divided by the original divisor (`spre') always works > out at within [0,0.5], so `squot' will be within [0,32768]. I guess the > static analyser is too dumb to figure it out, so I'll see how to paper it > over unless someone has a better proposal. These emails are a one time email so it's okay to ignore them if you want. regards, dan carpenter ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-17 13:23 ` Dan Carpenter 0 siblings, 0 replies; 17+ messages in thread From: Dan Carpenter @ 2022-02-17 13:23 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 1622 bytes --] On Thu, Feb 17, 2022 at 12:05:58PM +0000, Maciej W. Rozycki wrote: > On Thu, 17 Feb 2022, Dan Carpenter wrote: > > > url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 > > base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing > > config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp(a)intel.com/config ) > > compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 > > > > If you fix the issue, kindly add following tag as appropriate > > Reported-by: kernel test robot <lkp@intel.com> > > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > > > New smatch warnings: > > drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. > > drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. > > drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. > > These variables do get assigned to in the first iteration of the loop, > because the deviation calculated (`srem') is normalised to the range of > [0,spre/2] and that divided by the original divisor (`spre') always works > out at within [0,0.5], so `squot' will be within [0,32768]. I guess the > static analyser is too dumb to figure it out, so I'll see how to paper it > over unless someone has a better proposal. These emails are a one time email so it's okay to ignore them if you want. regards, dan carpenter ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-17 13:23 ` Dan Carpenter 0 siblings, 0 replies; 17+ messages in thread From: Dan Carpenter @ 2022-02-17 13:23 UTC (permalink / raw) To: kbuild [-- Attachment #1: Type: text/plain, Size: 1622 bytes --] On Thu, Feb 17, 2022 at 12:05:58PM +0000, Maciej W. Rozycki wrote: > On Thu, 17 Feb 2022, Dan Carpenter wrote: > > > url: https://github.com/0day-ci/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220212-164255 > > base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing > > config: x86_64-randconfig-m001 (https://download.01.org/0day-ci/archive/20220213/202202130027.ZKBCgtm5-lkp(a)intel.com/config ) > > compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 > > > > If you fix the issue, kindly add following tag as appropriate > > Reported-by: kernel test robot <lkp@intel.com> > > Reported-by: Dan Carpenter <dan.carpenter@oracle.com> > > > > New smatch warnings: > > drivers/tty/serial/8250/8250_pci.c:1171 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. > > drivers/tty/serial/8250/8250_pci.c:1172 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. > > drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. > > These variables do get assigned to in the first iteration of the loop, > because the deviation calculated (`srem') is normalised to the range of > [0,spre/2] and that divided by the original divisor (`spre') always works > out at within [0,0.5], so `squot' will be within [0,32768]. I guess the > static analyser is too dumb to figure it out, so I'll see how to paper it > over unless someone has a better proposal. These emails are a one time email so it's okay to ignore them if you want. regards, dan carpenter ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices 2022-02-17 13:23 ` Dan Carpenter @ 2022-02-21 15:56 ` Maciej W. Rozycki -1 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-21 15:56 UTC (permalink / raw) To: Dan Carpenter Cc: Greg Kroah-Hartman, kbuild, Jiri Slaby, lkp, kbuild-all, Andy Shevchenko, Mike Korreng, info, linux-serial, linux-kernel On Thu, 17 Feb 2022, Dan Carpenter wrote: > > These variables do get assigned to in the first iteration of the loop, > > because the deviation calculated (`srem') is normalised to the range of > > [0,spre/2] and that divided by the original divisor (`spre') always works > > out at within [0,0.5], so `squot' will be within [0,32768]. I guess the > > static analyser is too dumb to figure it out, so I'll see how to paper it > > over unless someone has a better proposal. > > These emails are a one time email so it's okay to ignore them if you > want. I'm inclined to leave it as it is then. Thank you for your explanation. Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices @ 2022-02-21 15:56 ` Maciej W. Rozycki 0 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-21 15:56 UTC (permalink / raw) To: kbuild-all [-- Attachment #1: Type: text/plain, Size: 660 bytes --] On Thu, 17 Feb 2022, Dan Carpenter wrote: > > These variables do get assigned to in the first iteration of the loop, > > because the deviation calculated (`srem') is normalised to the range of > > [0,spre/2] and that divided by the original divisor (`spre') always works > > out at within [0,0.5], so `squot' will be within [0,32768]. I guess the > > static analyser is too dumb to figure it out, so I'll see how to paper it > > over unless someone has a better proposal. > > These emails are a one time email so it's okay to ignore them if you > want. I'm inclined to leave it as it is then. Thank you for your explanation. Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs
@ 2022-02-12 8:41 Maciej W. Rozycki
2022-02-12 8:41 ` [PATCH v3 1/2] serial: 8250: Fold EndRun device support into OxSemi Tornado code Maciej W. Rozycki
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Maciej W. Rozycki @ 2022-02-12 8:41 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial,
linux-kernel
Hi,
Cc-ing the general contact point at EndRun for 1/2 of this series in case
the original submitters of the affected code are not there anymore after
those 7 years.
Here's v3 of the outstanding fixes for Oxford Semiconductor 950 UARTs.
As the change for the default FIFO rx trigger level has been already
merged with commit d7aff291d069 ("serial: 8250: Define RX trigger levels
for OxSemi 950 devices") only one patch of the original series remains.
However in the course of preparing v3 of that change I have noticed that
the EndRun device is actually also an OxSemi 952 device in disguise (note
that the OxSemi chips have fully customer-programmable PCI vendor:device
ID values). Therefore it requires a similar fix to the base baud rate as
with commit 6cbe45d8ac93 ("serial: 8250: Correct the clock for OxSemi
PCIe devices"), and also duplicate code can be removed.
I have therefore added a fix for the EndRun device as 1/2 in this version
and the original outstanding change is now 2/2, updated accordingly, also
for a change in the handling of the MCR made with commit b4a29b94804c
("serial: 8250: Move Alpha-specific quirk out of the core").
As noted in the course of v2 review I don't believe the Linux kernel has
a policy for any of its subsystems to require rewriting parts of existing
code to fix bugs or internal API deficiencies as a prerequisite for bug
fix (or even functional improvement) acceptance. Therefore I consider
this v3 of the series final and I am not going to continue pursuing this
submission any further unless there is an actual technical defect (a bug,
a coding style issue, etc.) within this series itself.
Please apply.
Maciej
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 1/2] serial: 8250: Fold EndRun device support into OxSemi Tornado code 2022-02-12 8:41 [PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki @ 2022-02-12 8:41 ` Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices Maciej W. Rozycki 2022-03-01 20:52 ` [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-12 8:41 UTC (permalink / raw) To: Greg Kroah-Hartman, Jiri Slaby Cc: Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial, linux-kernel The EndRun PTP/1588 dual serial port device is based on the Oxford Semiconductor OXPCIe952 UART device with the PCI vendor:device ID set for EndRun Technologies and uses the same sequence to determine the number of ports available. Despite that we have duplicate code specific to the EndRun device. Remove redundant code then and factor out OxSemi Tornado device detection. Also correct the baud base like with commit 6cbe45d8ac93 ("serial: 8250: Correct the clock for OxSemi PCIe devices") for the value of 3906250 rather than 4000000, obtained by dividing the 62.5MHz clock input by the default oversampling rate of 16. Finally move the EndRun vendor:device ID to <linux/pci_ids.h>. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Fixes: 1bc8cde46a159 ("8250_pci: Added driver for Endrun Technologies PTP PCIe card.") --- drivers/tty/serial/8250/8250_pci.c | 79 +++++++++++-------------------------- include/linux/pci_ids.h | 3 + 2 files changed, 28 insertions(+), 54 deletions(-) Index: linux-macro/drivers/tty/serial/8250/8250_pci.c =================================================================== --- linux-macro.orig/drivers/tty/serial/8250/8250_pci.c +++ linux-macro/drivers/tty/serial/8250/8250_pci.c @@ -994,41 +994,26 @@ static void pci_ite887x_exit(struct pci_ } /* - * EndRun Technologies. - * Determine the number of ports available on the device. + * Oxford Semiconductor Inc. + * Check if an OxSemi device is part of the Tornado range of devices. */ -#define PCI_VENDOR_ID_ENDRUN 0x7401 -#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 - -static int pci_endrun_init(struct pci_dev *dev) +static bool pci_oxsemi_tornado_p(struct pci_dev *dev) { - u8 __iomem *p; - unsigned long deviceID; - unsigned int number_uarts = 0; + /* OxSemi Tornado devices are all 0xCxxx */ + if (dev->vendor == PCI_VENDOR_ID_OXSEMI && + (dev->device & 0xf000) != 0xc000) + return false; - /* EndRun device is all 0xexxx */ + /* EndRun devices are all 0xExxx */ if (dev->vendor == PCI_VENDOR_ID_ENDRUN && - (dev->device & 0xf000) != 0xe000) - return 0; - - p = pci_iomap(dev, 0, 5); - if (p == NULL) - return -ENOMEM; + (dev->device & 0xf000) != 0xe000) + return false; - deviceID = ioread32(p); - /* EndRun device */ - if (deviceID == 0x07000200) { - number_uarts = ioread8(p + 4); - pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts); - } - pci_iounmap(dev, p); - return number_uarts; + return true; } /* - * Oxford Semiconductor Inc. - * Check that device is part of the Tornado range of devices, then determine - * the number of ports available on the device. + * Determine the number of ports available on a Tornado device. */ static int pci_oxsemi_tornado_init(struct pci_dev *dev) { @@ -1036,9 +1021,7 @@ static int pci_oxsemi_tornado_init(struc unsigned long deviceID; unsigned int number_uarts = 0; - /* OxSemi Tornado devices are all 0xCxxx */ - if (dev->vendor == PCI_VENDOR_ID_OXSEMI && - (dev->device & 0xF000) != 0xC000) + if (!pci_oxsemi_tornado_p(dev)) return 0; p = pci_iomap(dev, 0, 5); @@ -1049,7 +1032,10 @@ static int pci_oxsemi_tornado_init(struc /* Tornado device */ if (deviceID == 0x07000200) { number_uarts = ioread8(p + 4); - pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts); + pci_dbg(dev, "%d ports detected on %s PCI Express device\n", + number_uarts, + dev->vendor == PCI_VENDOR_ID_ENDRUN ? + "EndRun" : "Oxford"); } pci_iounmap(dev, p); return number_uarts; @@ -2244,7 +2230,7 @@ static struct pci_serial_quirk pci_seria .device = PCI_ANY_ID, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, - .init = pci_endrun_init, + .init = pci_oxsemi_tornado_init, .setup = pci_default_setup, }, /* @@ -2667,7 +2653,6 @@ enum pci_board_num_t { pbn_panacom2, pbn_panacom4, pbn_plx_romulus, - pbn_endrun_2_4000000, pbn_oxsemi, pbn_oxsemi_1_3906250, pbn_oxsemi_2_3906250, @@ -3190,20 +3175,6 @@ static struct pciserial_board pci_boards }, /* - * EndRun Technologies - * Uses the size of PCI Base region 0 to - * signal now many ports are available - * 2 port 952 Uart support - */ - [pbn_endrun_2_4000000] = { - .flags = FL_BASE0, - .num_ports = 2, - .base_baud = 4000000, - .uart_offset = 0x200, - .first_offset = 0x1000, - }, - - /* * This board uses the size of PCI Base region 0 to * signal now many ports are available */ @@ -4123,13 +4094,6 @@ static const struct pci_device_id serial 0x10b5, 0x106a, 0, 0, pbn_plx_romulus }, /* - * EndRun Technologies. PCI express device range. - * EndRun PTP/1588 has 2 Native UARTs. - */ - { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, - PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_endrun_2_4000000 }, - /* * Quatech cards. These actually have configurable clocks but for * now we just use the default. * @@ -4390,6 +4354,13 @@ static const struct pci_device_id serial { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, pbn_oxsemi_2_3906250 }, + /* + * EndRun Technologies. PCI express device range. + * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. + */ + { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, + pbn_oxsemi_2_3906250 }, /* * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, Index: linux-macro/include/linux/pci_ids.h =================================================================== --- linux-macro.orig/include/linux/pci_ids.h +++ linux-macro/include/linux/pci_ids.h @@ -2614,6 +2614,9 @@ #define PCI_DEVICE_ID_DCI_PCCOM8 0x0002 #define PCI_DEVICE_ID_DCI_PCCOM2 0x0004 +#define PCI_VENDOR_ID_ENDRUN 0x7401 +#define PCI_DEVICE_ID_ENDRUN_1588 0xe100 + #define PCI_VENDOR_ID_INTEL 0x8086 #define PCI_DEVICE_ID_INTEL_EESSC 0x0008 #define PCI_DEVICE_ID_INTEL_PXHD_0 0x0320 ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices 2022-02-12 8:41 [PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 1/2] serial: 8250: Fold EndRun device support into OxSemi Tornado code Maciej W. Rozycki @ 2022-02-12 8:41 ` Maciej W. Rozycki 2022-02-12 14:36 ` Andy Shevchenko 2022-03-01 20:52 ` [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2 siblings, 1 reply; 17+ messages in thread From: Maciej W. Rozycki @ 2022-02-12 8:41 UTC (permalink / raw) To: Greg Kroah-Hartman, Jiri Slaby Cc: Andy Shevchenko, Mike Skoog, Mike Korreng, info, linux-serial, linux-kernel Oxford Semiconductor PCIe (Tornado) 950 serial port devices are driven by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock. We currently drive the device using its default oversampling rate of 16 and the clock prescaler disabled, consequently yielding the baud base of 3906250. This base is inadequate for some of the high-speed baud rates such as 460800bps, for which the closest rate possible can be obtained by dividing the baud base by 8, yielding the baud rate of 488281.25bps, which is off by 5.9638%. This is enough for data communication to break with the remote end talking actual 460800bps where missed stop bits have been observed. We can do better however, by taking advantage of a reduced oversampling rate, which can be set to any integer value from 4 to 16 inclusive by programming the TCR register, and by using the clock prescaler, which can be set to any value from 1 to 63.875 in increments of 0.125 in the CPR/CPR2 register pair. The prescaler has to be explicitly enabled though by setting bit 7 in the MCR or otherwise it is bypassed (in the enhanced mode that we enable) as if the value of 1 was used. Make use of these features then as follows: - Set the baud base to 15625000, reflecting the minimum oversampling rate of 4 with the clock prescaler and divisor both set to 1. - Override the `set_mctrl' and set the MCR shadow there so as to have MCR[7] always set and have the 8250 core propagate this settings; also make the console restorer use this shadow. - Override the `get_divisor' handler and determine a good combination of parameters by using a lookup table with predetermined value pairs of the oversampling rate and the clock prescaler and finding a pair that divides the input clock such that the quotient, when rounded to the nearest integer, deviates the least from the exact result. Calculate the clock divisor accordingly. Scale the resulting oversampling rate (only by powers of two) if possible so as to maximise it, reducing the divisor accordingly, and avoid a divisor overflow for very low baud rates by scaling the oversampling rate and/or the prescaler even if that causes some accuracy loss. Also handle the historic spd_cust feature so as to allow one to set all the three parameters manually to arbitrary values, by keeping the low 16 bits for the divisor and then putting TCR in bits 19:16 and CPR/CPR2 in bits 28:20, sanitising the bit pattern supplied such as to clamp CPR/CPR2 values between 0.000 and 0.875 inclusive to 33.875. This preserves compatibility with any existing setups, that is where requesting a custom divisor that only has any bits set among the low 16 the oversampling rate of 16 and the clock prescaler of 33.875 will be used as with the original 8250. Finally abuse the `frac' argument to store the determined bit patterns for the TCR, CPR and CPR2 registers. - Override the `set_divisor' handler so as to set the TCR, CPR and CPR2 registers from the `frac' value supplied. Set the divisor as usually. With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX limitation imposed by `serial8250_get_baud_rate' standard baud rates below 300bps become unavailable in the regular way, e.g. the rate of 200bps requires the baud base to be divided by 78125 and that is beyond the unsigned 16-bit range. The historic spd_cust feature can still be used to obtain such rates if so required. See Documentation/tty/device_drivers/oxsemi-tornado.rst for more details. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> --- Changes from v2: - Rework for commit b4a29b94804c ("serial: 8250: Move Alpha-specific quirk out of the core"), also meaning the `-Woverflow' hack is not needed anymore. - Adjust `serial8250_console_restore' to OR in `up->mcr' like in `serial8250_do_set_mctrl'. - Default to the prescaler of 33.875 for values requested below 1 via the spd_cust feature for 8250 compatibility. - Follow the arrangement from `pci_oxsemi_tornado_init' to also correctly handle non-OxSemi PCI vendor:device IDs in `pci_oxsemi_tornado_setup'; NB these IDs are fully customer-programmable in OxSemi devices and ones based on the OxSemi vendor IDs are only the device defaults. - Factor in EndRun device handling unification. - Move figures to Documentation/tty/device_drivers/oxsemi-tornado.rst. Changes from v1: - Kill a silly `-Woverflow' warning. --- Documentation/tty/device_drivers/oxsemi-tornado.rst | 129 +++++++ drivers/tty/serial/8250/8250.h | 23 + drivers/tty/serial/8250/8250_pci.c | 338 +++++++++++++++----- drivers/tty/serial/8250/8250_port.c | 23 - 4 files changed, 423 insertions(+), 90 deletions(-) Index: linux-macro/Documentation/tty/device_drivers/oxsemi-tornado.rst =================================================================== --- /dev/null +++ linux-macro/Documentation/tty/device_drivers/oxsemi-tornado.rst @@ -0,0 +1,129 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================================================================== +Notes on Oxford Semiconductor PCIe (Tornado) 950 serial port devices +==================================================================== + +Oxford Semiconductor PCIe (Tornado) 950 serial port devices are driven +by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock. + +The baud rate produced by the baud generator is obtained from this input +frequency by dividing it by the clock prescaler, which can be set to any +value from 1 to 63.875 in increments of 0.125, and then the usual 16-bit +divisor is used as with the original 8250, to divide the frequency by a +value from 1 to 65535. Finally a programmable oversampling rate is used +that can take any value from 4 to 16 to divide the frequency further and +determine the actual baud rate used. Baud rates from 15625000bps down +to 0.933bps can be obtained this way. + +By default the oversampling rate is set to 16 and the clock prescaler is +set to 33.875, meaning that the frequency to be used as the reference +for the usual 16-bit divisor is 115313.653, which is close enough to the +frequency of 115200 used by the original 8250 for the same values to be +used for the divisor to obtain the requested baud rates by software that +is unaware of the extra clock controls available. + +The oversampling rate is programmed with the TCR register and the clock +prescaler is programmed with the CPR/CPR2 register pair[1][2][3][4]. +To switch away from the default value of 33.875 for the prescaler the +the enhanced mode has to be explicitly enabled though, by setting bit 4 +of the EFR. In that mode setting bit 7 in the MCR enables the prescaler +or otherwise it is bypassed as if the value of 1 was used. Additionally +writing any value to CPR clears CPR2 for compatibility with old software +written for older conventional PCI Oxford Semiconductor devices that do +not have the extra prescaler's 9th bit in CPR2, so the CPR/CPR2 register +pair has to be programmed in the right order. + +By using these parameters rates from 15625000bps down to 1bps can be +obtained, with either exact or highly-accurate actual bit rates for +standard and many non-standard rates. + +Here are the figures for the standard and some non-standard baud rates +(including those quoted in Oxford Semiconductor documentation), giving +the requested rate (r), the actual rate yielded (a) and its deviation +from the requested rate (d), and the values of the oversampling rate +(tcr), the clock prescaler (cpr) and the divisor (div) produced by the +new `get_divisor' handler: + +r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1 +r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1 +r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1 +r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1 +r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1 +r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1 +r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1 +r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1 +r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1 +r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1 +r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1 +r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1 +r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1 +r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1 +r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2 +r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2 +r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5 +r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5 +r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31 +r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35 +r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30 +r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105 +r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643 +r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647 +r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286 +r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294 +r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215 +r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625 +r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245 +r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153 +r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348 +r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461 +r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500 +r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500 +r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828 +r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828 +r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154 + +With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX +limitation imposed by `serial8250_get_baud_rate' standard baud rates +below 300bps become unavailable in the regular way, e.g. the rate of +200bps requires the baud base to be divided by 78125 and that is beyond +the unsigned 16-bit range. The historic spd_cust feature can still be +used by encoding the values for, the prescaler, the oversampling rate +and the clock divisor (DLM/DLL) as follows to obtain such rates if so +required: + + 31 29 28 20 19 16 15 0 ++-----+-----------------+-------+-------------------------------+ +|0 0 0| CPR2:CPR | TCR | DLM:DLL | ++-----+-----------------+-------+-------------------------------+ + +Use a value such encoded for the `custom_divisor' field along with the +ASYNC_SPD_CUST flag set in the `flags' field in `struct serial_struct' +passed with the TIOCSSERIAL ioctl(2), such as with the setserial(8) +utility and its `divisor' and `spd_cust' parameters, and the select +the baud rate of 38400bps. Note that the value of 0 in TCR sets the +oversampling rate to 16 and prescaler values below 1 in CPR2/CPR are +clamped by the driver to 1. + +For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL +respectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value, +the oversampling rate and the clock divisor of 62.500, 16 and 1250 +respectively. These parameters will set the baud rate for the serial +port to 62500000 / 62.500 / 1250 / 16 = 50bps. + +References: + +[1] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor, + Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65 + +[2] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port", + Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode", + p. 20 + +[3] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford + Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20 + +[4] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford + Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20 + +Maciej W. Rozycki <macro@orcam.me.uk> Index: linux-macro/drivers/tty/serial/8250/8250.h =================================================================== --- linux-macro.orig/drivers/tty/serial/8250/8250.h +++ linux-macro/drivers/tty/serial/8250/8250.h @@ -120,6 +120,29 @@ static inline void serial_out(struct uar up->port.serial_out(&up->port, offset, value); } +/* + * For the 16C950 + */ +static inline void serial_icr_write(struct uart_8250_port *up, + int offset, int value) +{ + serial_out(up, UART_SCR, offset); + serial_out(up, UART_ICR, value); +} + +static inline unsigned int serial_icr_read(struct uart_8250_port *up, + int offset) +{ + unsigned int value; + + serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); + serial_out(up, UART_SCR, offset); + value = serial_in(up, UART_ICR); + serial_icr_write(up, UART_ACR, up->acr); + + return value; +} + void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p); static inline int serial_dl_read(struct uart_8250_port *up) Index: linux-macro/drivers/tty/serial/8250/8250_pci.c =================================================================== --- linux-macro.orig/drivers/tty/serial/8250/8250_pci.c +++ linux-macro/drivers/tty/serial/8250/8250_pci.c @@ -1041,6 +1041,208 @@ static int pci_oxsemi_tornado_init(struc return number_uarts; } +/* Tornado-specific constants for the TCR and CPR registers; see below. */ +#define OXSEMI_TORNADO_TCR_MASK 0xf +#define OXSEMI_TORNADO_CPR_MASK 0x1ff +#define OXSEMI_TORNADO_CPR_MIN 0x008 +#define OXSEMI_TORNADO_CPR_DEF 0x10f + +/* + * Determine the oversampling rate, the clock prescaler, and the clock + * divisor for the requested baud rate. The clock rate is 62.5 MHz, + * which is four times the baud base, and the prescaler increments in + * steps of 1/8. Therefore to make calculations on integers we need + * to use a scaled clock rate, which is the baud base multiplied by 32 + * (or our assumed UART clock rate multiplied by 2). + * + * The allowed oversampling rates are from 4 up to 16 inclusive (values + * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows + * values between 1.000 and 63.875 inclusive (operation for values from + * 0.000 to 0.875 has not been specified). The clock divisor is the usual + * unsigned 16-bit integer. + * + * For the most accurate baud rate we use a table of predetermined + * oversampling rates and clock prescalers that records all possible + * products of the two parameters in the range from 4 up to 255 inclusive, + * and additionally 335 for the 1500000bps rate, with the prescaler scaled + * by 8. The table is sorted by the decreasing value of the oversampling + * rate and ties are resolved by sorting by the decreasing value of the + * product. This way preference is given to higher oversampling rates. + * + * We iterate over the table and choose the product of an oversampling + * rate and a clock prescaler that gives the lowest integer division + * result deviation, or if an exact integer divider is found we stop + * looking for it right away. We do some fixup if the resulting clock + * divisor required would be out of its unsigned 16-bit integer range. + * + * Finally we abuse the supposed fractional part returned to encode the + * 4-bit value of the oversampling rate and the 9-bit value of the clock + * prescaler which will end up in the TCR and CPR/CPR2 registers. + */ +static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, + unsigned int baud, + unsigned int *frac) +{ + static u8 p[][2] = { + { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, + { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, + { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, + { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, + { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, + { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, + { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, + { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, + { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, + { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, + { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, + { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, + { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, + { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, + { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, + { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, + { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, + { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, + { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, + { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, + { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, + { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, + { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, + { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, + { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, + { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, + { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, + { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, + { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, + { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, + { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, + { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, + { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, + { 4, 9, }, { 4, 8, }, + }; + /* Scale the quotient for comparison to get the fractional part. */ + const unsigned int quot_scale = 65536; + unsigned int sclk = port->uartclk * 2; + unsigned int sdiv = (sclk + (baud / 2)) / baud; + unsigned int best_squot; + unsigned int squot; + unsigned int quot; + u16 cpr; + u8 tcr; + int i; + + /* Old custom speed handling. */ + if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { + unsigned int cust_div = port->custom_divisor; + + quot = cust_div & UART_DIV_MAX; + tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; + cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; + if (cpr < OXSEMI_TORNADO_CPR_MIN) + cpr = OXSEMI_TORNADO_CPR_DEF; + } else { + best_squot = quot_scale; + for (i = 0; i < ARRAY_SIZE(p); i++) { + unsigned int spre; + unsigned int srem; + u8 cp; + u8 tc; + + tc = p[i][0]; + cp = p[i][1]; + spre = tc * cp; + + srem = sdiv % spre; + if (srem > spre / 2) + srem = spre - srem; + squot = (srem * quot_scale + spre / 2) / spre; + + if (srem == 0) { + tcr = tc; + cpr = cp; + quot = sdiv / spre; + break; + } else if (squot < best_squot) { + best_squot = squot; + tcr = tc; + cpr = cp; + quot = (sdiv + spre / 2) / spre; + } + } + while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && + quot % 2 == 0) { + quot >>= 1; + tcr <<= 1; + } + while (quot > UART_DIV_MAX) { + if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { + quot >>= 1; + tcr <<= 1; + } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { + quot >>= 1; + cpr <<= 1; + } else { + quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; + cpr = OXSEMI_TORNADO_CPR_MASK; + } + } + } + + *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); + return quot; +} + +/* + * Set the oversampling rate in the transmitter clock cycle register (TCR), + * the clock prescaler in the clock prescaler register (CPR and CPR2), and + * the clock divisor in the divisor latch (DLL and DLM). Note that for + * backwards compatibility any write to CPR clears CPR2 and therefore CPR + * has to be written first, followed by CPR2, which occupies the location + * of CKS used with earlier UART designs. + */ +static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, + unsigned int baud, + unsigned int quot, + unsigned int quot_frac) +{ + struct uart_8250_port *up = up_to_u8250p(port); + u8 cpr2 = quot_frac >> 16; + u8 cpr = quot_frac >> 8; + u8 tcr = quot_frac; + + serial_icr_write(up, UART_TCR, tcr); + serial_icr_write(up, UART_CPR, cpr); + serial_icr_write(up, UART_CKS, cpr2); + serial8250_do_set_divisor(port, baud, quot, 0); +} + +/* + * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate + * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. + */ +static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, + unsigned int mctrl) +{ + struct uart_8250_port *up = up_to_u8250p(port); + + up->mcr |= UART_MCR_CLKSEL; + serial8250_do_set_mctrl(port, mctrl); +} + +static int pci_oxsemi_tornado_setup(struct serial_private *priv, + const struct pciserial_board *board, + struct uart_8250_port *up, int idx) +{ + struct pci_dev *dev = priv->dev; + + if (pci_oxsemi_tornado_p(dev)) { + up->port.get_divisor = pci_oxsemi_tornado_get_divisor; + up->port.set_divisor = pci_oxsemi_tornado_set_divisor; + up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; + } + + return pci_default_setup(priv, board, up, idx); +} + static int pci_asix_setup(struct serial_private *priv, const struct pciserial_board *board, struct uart_8250_port *port, int idx) @@ -2242,7 +2444,7 @@ static struct pci_serial_quirk pci_seria .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .init = pci_oxsemi_tornado_init, - .setup = pci_default_setup, + .setup = pci_oxsemi_tornado_setup, }, { .vendor = PCI_VENDOR_ID_MAINPINE, @@ -2250,7 +2452,7 @@ static struct pci_serial_quirk pci_seria .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, .init = pci_oxsemi_tornado_init, - .setup = pci_default_setup, + .setup = pci_oxsemi_tornado_setup, }, { .vendor = PCI_VENDOR_ID_DIGI, @@ -2258,7 +2460,7 @@ static struct pci_serial_quirk pci_seria .subvendor = PCI_SUBVENDOR_ID_IBM, .subdevice = PCI_ANY_ID, .init = pci_oxsemi_tornado_init, - .setup = pci_default_setup, + .setup = pci_oxsemi_tornado_setup, }, { .vendor = PCI_VENDOR_ID_INTEL, @@ -2575,7 +2777,7 @@ enum pci_board_num_t { pbn_b0_2_1843200, pbn_b0_4_1843200, - pbn_b0_1_3906250, + pbn_b0_1_15625000, pbn_b0_bt_1_115200, pbn_b0_bt_2_115200, @@ -2654,10 +2856,10 @@ enum pci_board_num_t { pbn_panacom4, pbn_plx_romulus, pbn_oxsemi, - pbn_oxsemi_1_3906250, - pbn_oxsemi_2_3906250, - pbn_oxsemi_4_3906250, - pbn_oxsemi_8_3906250, + pbn_oxsemi_1_15625000, + pbn_oxsemi_2_15625000, + pbn_oxsemi_4_15625000, + pbn_oxsemi_8_15625000, pbn_intel_i960, pbn_sgi_ioc3, pbn_computone_4, @@ -2800,10 +3002,10 @@ static struct pciserial_board pci_boards .uart_offset = 8, }, - [pbn_b0_1_3906250] = { + [pbn_b0_1_15625000] = { .flags = FL_BASE0, .num_ports = 1, - .base_baud = 3906250, + .base_baud = 15625000, .uart_offset = 8, }, @@ -3184,31 +3386,31 @@ static struct pciserial_board pci_boards .base_baud = 115200, .uart_offset = 8, }, - [pbn_oxsemi_1_3906250] = { + [pbn_oxsemi_1_15625000] = { .flags = FL_BASE0, .num_ports = 1, - .base_baud = 3906250, + .base_baud = 15625000, .uart_offset = 0x200, .first_offset = 0x1000, }, - [pbn_oxsemi_2_3906250] = { + [pbn_oxsemi_2_15625000] = { .flags = FL_BASE0, .num_ports = 2, - .base_baud = 3906250, + .base_baud = 15625000, .uart_offset = 0x200, .first_offset = 0x1000, }, - [pbn_oxsemi_4_3906250] = { + [pbn_oxsemi_4_15625000] = { .flags = FL_BASE0, .num_ports = 4, - .base_baud = 3906250, + .base_baud = 15625000, .uart_offset = 0x200, .first_offset = 0x1000, }, - [pbn_oxsemi_8_3906250] = { + [pbn_oxsemi_8_15625000] = { .flags = FL_BASE0, .num_ports = 8, - .base_baud = 3906250, + .base_baud = 15625000, .uart_offset = 0x200, .first_offset = 0x1000, }, @@ -4202,165 +4404,165 @@ static const struct pci_device_id serial */ { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_b0_1_3906250 }, + pbn_b0_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_2_3906250 }, + pbn_oxsemi_2_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_2_3906250 }, + pbn_oxsemi_2_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_4_3906250 }, + pbn_oxsemi_4_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_4_3906250 }, + pbn_oxsemi_4_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_8_3906250 }, + pbn_oxsemi_8_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_8_3906250 }, + pbn_oxsemi_8_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, /* * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado */ { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, - pbn_oxsemi_1_3906250 }, + pbn_oxsemi_1_15625000 }, { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, - pbn_oxsemi_2_3906250 }, + pbn_oxsemi_2_15625000 }, { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, - pbn_oxsemi_4_3906250 }, + pbn_oxsemi_4_15625000 }, { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, - pbn_oxsemi_8_3906250 }, + pbn_oxsemi_8_15625000 }, /* * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado */ { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, - pbn_oxsemi_2_3906250 }, + pbn_oxsemi_2_15625000 }, /* * EndRun Technologies. PCI express device range. * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. */ { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, - pbn_oxsemi_2_3906250 }, + pbn_oxsemi_2_15625000 }, /* * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, Index: linux-macro/drivers/tty/serial/8250/8250_port.c =================================================================== --- linux-macro.orig/drivers/tty/serial/8250/8250_port.c +++ linux-macro/drivers/tty/serial/8250/8250_port.c @@ -530,27 +530,6 @@ serial_port_out_sync(struct uart_port *p } /* - * For the 16C950 - */ -static void serial_icr_write(struct uart_8250_port *up, int offset, int value) -{ - serial_out(up, UART_SCR, offset); - serial_out(up, UART_ICR, value); -} - -static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) -{ - unsigned int value; - - serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); - serial_out(up, UART_SCR, offset); - value = serial_in(up, UART_ICR); - serial_icr_write(up, UART_ACR, up->acr); - - return value; -} - -/* * FIFO support. */ static void serial8250_clear_fifos(struct uart_8250_port *p) @@ -3322,7 +3301,7 @@ static void serial8250_console_restore(s serial8250_set_divisor(port, baud, quot, frac); serial_port_out(port, UART_LCR, up->lcr); - serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS); + serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS); } /* ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices 2022-02-12 8:41 ` [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices Maciej W. Rozycki @ 2022-02-12 14:36 ` Andy Shevchenko 0 siblings, 0 replies; 17+ messages in thread From: Andy Shevchenko @ 2022-02-12 14:36 UTC (permalink / raw) To: Maciej W. Rozycki Cc: Greg Kroah-Hartman, Jiri Slaby, Mike Skoog, Mike Korreng, info, open list:SERIAL DRIVERS, Linux Kernel Mailing List On Sat, Feb 12, 2022 at 10:41 AM Maciej W. Rozycki <macro@orcam.me.uk> wrote: > > Oxford Semiconductor PCIe (Tornado) 950 serial port devices are driven > by a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock. > > We currently drive the device using its default oversampling rate of 16 > and the clock prescaler disabled, consequently yielding the baud base of > 3906250. This base is inadequate for some of the high-speed baud rates > such as 460800bps, for which the closest rate possible can be obtained > by dividing the baud base by 8, yielding the baud rate of 488281.25bps, > which is off by 5.9638%. This is enough for data communication to break > with the remote end talking actual 460800bps where missed stop bits have > been observed. > > We can do better however, by taking advantage of a reduced oversampling > rate, which can be set to any integer value from 4 to 16 inclusive by > programming the TCR register, and by using the clock prescaler, which > can be set to any value from 1 to 63.875 in increments of 0.125 in the > CPR/CPR2 register pair. The prescaler has to be explicitly enabled > though by setting bit 7 in the MCR or otherwise it is bypassed (in the > enhanced mode that we enable) as if the value of 1 was used. > > Make use of these features then as follows: > > - Set the baud base to 15625000, reflecting the minimum oversampling > rate of 4 with the clock prescaler and divisor both set to 1. > > - Override the `set_mctrl' and set the MCR shadow there so as to have > MCR[7] always set and have the 8250 core propagate this settings; also > make the console restorer use this shadow. > > - Override the `get_divisor' handler and determine a good combination of > parameters by using a lookup table with predetermined value pairs of > the oversampling rate and the clock prescaler and finding a pair that > divides the input clock such that the quotient, when rounded to the > nearest integer, deviates the least from the exact result. Calculate > the clock divisor accordingly. > > Scale the resulting oversampling rate (only by powers of two) if > possible so as to maximise it, reducing the divisor accordingly, and > avoid a divisor overflow for very low baud rates by scaling the > oversampling rate and/or the prescaler even if that causes some > accuracy loss. > > Also handle the historic spd_cust feature so as to allow one to set > all the three parameters manually to arbitrary values, by keeping the > low 16 bits for the divisor and then putting TCR in bits 19:16 and > CPR/CPR2 in bits 28:20, sanitising the bit pattern supplied such as > to clamp CPR/CPR2 values between 0.000 and 0.875 inclusive to 33.875. > This preserves compatibility with any existing setups, that is where > requesting a custom divisor that only has any bits set among the low > 16 the oversampling rate of 16 and the clock prescaler of 33.875 will > be used as with the original 8250. > > Finally abuse the `frac' argument to store the determined bit patterns > for the TCR, CPR and CPR2 registers. > > - Override the `set_divisor' handler so as to set the TCR, CPR and CPR2 > registers from the `frac' value supplied. Set the divisor as usually. > > With the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX > limitation imposed by `serial8250_get_baud_rate' standard baud rates > below 300bps become unavailable in the regular way, e.g. the rate of > 200bps requires the baud base to be divided by 78125 and that is beyond > the unsigned 16-bit range. The historic spd_cust feature can still be > used to obtain such rates if so required. > > See Documentation/tty/device_drivers/oxsemi-tornado.rst for more details. ... > + /* Old custom speed handling. */ Exactly and we do not want to see this in the new code. > + if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { > + unsigned int cust_div = port->custom_divisor; > + > + quot = cust_div & UART_DIV_MAX; > + tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; > + cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; > + if (cpr < OXSEMI_TORNADO_CPR_MIN) > + cpr = OXSEMI_TORNADO_CPR_DEF; > + } else { I'll read and comment on the rest later on (hopefully next week). P.S. I still think that overloading 8250_pci with custom quirks is not a good idea. -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs 2022-02-12 8:41 [PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 1/2] serial: 8250: Fold EndRun device support into OxSemi Tornado code Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices Maciej W. Rozycki @ 2022-03-01 20:52 ` Maciej W. Rozycki 2022-03-18 12:10 ` Greg Kroah-Hartman 2 siblings, 1 reply; 17+ messages in thread From: Maciej W. Rozycki @ 2022-03-01 20:52 UTC (permalink / raw) To: Greg Kroah-Hartman, Jiri Slaby Cc: Andy Shevchenko, linux-serial, linux-kernel On Sat, 12 Feb 2022, Maciej W. Rozycki wrote: > Here's v3 of the outstanding fixes for Oxford Semiconductor 950 UARTs. > As the change for the default FIFO rx trigger level has been already > merged with commit d7aff291d069 ("serial: 8250: Define RX trigger levels > for OxSemi 950 devices") only one patch of the original series remains. Ping for: <https://lore.kernel.org/lkml/alpine.DEB.2.21.2202100424280.34636@angie.orcam.me.uk/> Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs 2022-03-01 20:52 ` [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki @ 2022-03-18 12:10 ` Greg Kroah-Hartman 2022-03-31 7:12 ` Maciej W. Rozycki 0 siblings, 1 reply; 17+ messages in thread From: Greg Kroah-Hartman @ 2022-03-18 12:10 UTC (permalink / raw) To: Maciej W. Rozycki; +Cc: Jiri Slaby, Andy Shevchenko, linux-serial, linux-kernel On Tue, Mar 01, 2022 at 08:52:25PM +0000, Maciej W. Rozycki wrote: > On Sat, 12 Feb 2022, Maciej W. Rozycki wrote: > > > Here's v3 of the outstanding fixes for Oxford Semiconductor 950 UARTs. > > As the change for the default FIFO rx trigger level has been already > > merged with commit d7aff291d069 ("serial: 8250: Define RX trigger levels > > for OxSemi 950 devices") only one patch of the original series remains. > > Ping for: > > <https://lore.kernel.org/lkml/alpine.DEB.2.21.2202100424280.34636@angie.orcam.me.uk/> These aren't in my review queue, can you resend? thanks, greg k-h ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs 2022-03-18 12:10 ` Greg Kroah-Hartman @ 2022-03-31 7:12 ` Maciej W. Rozycki 0 siblings, 0 replies; 17+ messages in thread From: Maciej W. Rozycki @ 2022-03-31 7:12 UTC (permalink / raw) To: Greg Kroah-Hartman Cc: Jiri Slaby, Andy Shevchenko, linux-serial, linux-kernel On Fri, 18 Mar 2022, Greg Kroah-Hartman wrote: > > > Here's v3 of the outstanding fixes for Oxford Semiconductor 950 UARTs. > > > As the change for the default FIFO rx trigger level has been already > > > merged with commit d7aff291d069 ("serial: 8250: Define RX trigger levels > > > for OxSemi 950 devices") only one patch of the original series remains. > > > > Ping for: > > > > <https://lore.kernel.org/lkml/alpine.DEB.2.21.2202100424280.34636@angie.orcam.me.uk/> > > These aren't in my review queue, can you resend? Reposted now, thanks! Maciej ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-03-31 7:13 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-12 18:17 [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices kernel test robot 2022-02-17 9:23 ` Dan Carpenter 2022-02-17 9:23 ` Dan Carpenter 2022-02-17 12:05 ` Maciej W. Rozycki 2022-02-17 12:05 ` Maciej W. Rozycki 2022-02-17 13:23 ` Dan Carpenter 2022-02-17 13:23 ` Dan Carpenter 2022-02-17 13:23 ` Dan Carpenter 2022-02-21 15:56 ` Maciej W. Rozycki 2022-02-21 15:56 ` Maciej W. Rozycki -- strict thread matches above, loose matches on Subject: below -- 2022-02-12 8:41 [PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 1/2] serial: 8250: Fold EndRun device support into OxSemi Tornado code Maciej W. Rozycki 2022-02-12 8:41 ` [PATCH v3 2/2] serial: 8250: Add proper clock handling for OxSemi PCIe devices Maciej W. Rozycki 2022-02-12 14:36 ` Andy Shevchenko 2022-03-01 20:52 ` [PING][PATCH v3 0/2] serial: 8250: Fixes for Oxford Semiconductor 950 UARTs Maciej W. Rozycki 2022-03-18 12:10 ` Greg Kroah-Hartman 2022-03-31 7:12 ` Maciej W. Rozycki
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.