[PATCH 0/4] Configure Zicbo[m|z] and Svpbmt in menvcfg CSR

[PATCH 0/4] Configure Zicbo[m|z] and Svpbmt in menvcfg CSR

[Anup Patel]

Lower privilege modes (S and U) can use Zicbo[m|z] and Svpbmt extensions
only if these extensions are configured/enabled by M-mode firmware hence
this series.

The PATCH2 is adapted from Atish's Sstc series to avoid duplicate work.

These patches can be found in pbmt_cbo_v1 branch at:
https://github.com/avpatel/opensbi.git

Anup Patel (3):
  include: Add defines for [m|h|s]envcfg CSRs
  lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR
  lib: sbi: Enable Svpbmt extension in the menvcfg CSR

Atish Patra (1):
  lib: sbi: Detect menvcfg CSR at boot time

 include/sbi/riscv_encoding.h | 27 +++++++++++++++++++
 include/sbi/sbi_hart.h       |  4 ++-
 lib/sbi/sbi_hart.c           | 52 +++++++++++++++++++++++++++++++++++-
 3 files changed, 81 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs

[Anup Patel]

The latest RISC-V privileged specification introduces xenvcfg CSRs
to enable/disable certain features/extensions for lower privilege
modes. This patch adds defines for these new [m|h|s]envcfg CSRs.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index 574d1c3..c02aa8f 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -203,6 +203,22 @@
 
 #define MHPMEVENT_SSCOF_MASK		_ULL(0xFFFF000000000000)
 
+#if __riscv_xlen > 32
+#define ENVCFG_STCE			(_ULL(1) << 63)
+#define ENVCFG_PBMTE			(_ULL(1) << 62)
+#else
+#define ENVCFGH_STCE			(_UL(1) << 31)
+#define ENVCFGH_PBMTE			(_UL(1) << 30)
+#endif
+#define ENVCFG_CBZE			(_UL(1) << 7)
+#define ENVCFG_CBCFE			(_UL(1) << 6)
+#define ENVCFG_CBIE_SHIFT		4
+#define ENVCFG_CBIE			(_UL(0x3) << ENVCFG_CBIE_SHIFT)
+#define ENVCFG_CBIE_ILL			_UL(0x0)
+#define ENVCFG_CBIE_FLUSH		_UL(0x1)
+#define ENVCFG_CBIE_INV			_UL(0x3)
+#define ENVCFG_FIOM			_UL(0x1)
+
 /* ===== User-level CSRs ===== */
 
 /* User Trap Setup (N-extension) */
@@ -298,6 +314,9 @@
 #define CSR_STVEC			0x105
 #define CSR_SCOUNTEREN			0x106
 
+/* Supervisor Configuration */
+#define CSR_SENVCFG			0x10a
+
 /* Supervisor Trap Handling */
 #define CSR_SSCRATCH			0x140
 #define CSR_SEPC			0x141
@@ -336,6 +355,10 @@
 #define CSR_HCOUNTEREN			0x606
 #define CSR_HGEIE			0x607
 
+/* Hypervisor Configuration */
+#define CSR_HENVCFG			0x60a
+#define CSR_HENVCFGH			0x61a
+
 /* Hypervisor Trap Handling (H-extension) */
 #define CSR_HTVAL			0x643
 #define CSR_HIP				0x644
@@ -408,6 +431,10 @@
 #define CSR_MCOUNTEREN			0x306
 #define CSR_MSTATUSH			0x310
 
+/* Machine Configuration */
+#define CSR_MENVCFG			0x30a
+#define CSR_MENVCFGH			0x31a
+
 /* Machine Trap Handling */
 #define CSR_MSCRATCH			0x340
 #define CSR_MEPC			0x341
-- 
2.25.1

[PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs

[Atish Patra]

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The latest RISC-V privileged specification introduces xenvcfg CSRs
> to enable/disable certain features/extensions for lower privilege
> modes. This patch adds defines for these new [m|h|s]envcfg CSRs.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 574d1c3..c02aa8f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -203,6 +203,22 @@
>
>  #define MHPMEVENT_SSCOF_MASK           _ULL(0xFFFF000000000000)
>
> +#if __riscv_xlen > 32
> +#define ENVCFG_STCE                    (_ULL(1) << 63)
> +#define ENVCFG_PBMTE                   (_ULL(1) << 62)
> +#else
> +#define ENVCFGH_STCE                   (_UL(1) << 31)
> +#define ENVCFGH_PBMTE                  (_UL(1) << 30)
> +#endif
> +#define ENVCFG_CBZE                    (_UL(1) << 7)
> +#define ENVCFG_CBCFE                   (_UL(1) << 6)
> +#define ENVCFG_CBIE_SHIFT              4
> +#define ENVCFG_CBIE                    (_UL(0x3) << ENVCFG_CBIE_SHIFT)
> +#define ENVCFG_CBIE_ILL                        _UL(0x0)
> +#define ENVCFG_CBIE_FLUSH              _UL(0x1)
> +#define ENVCFG_CBIE_INV                        _UL(0x3)
> +#define ENVCFG_FIOM                    _UL(0x1)
> +
>  /* ===== User-level CSRs ===== */
>
>  /* User Trap Setup (N-extension) */
> @@ -298,6 +314,9 @@
>  #define CSR_STVEC                      0x105
>  #define CSR_SCOUNTEREN                 0x106
>
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG                    0x10a
> +
>  /* Supervisor Trap Handling */
>  #define CSR_SSCRATCH                   0x140
>  #define CSR_SEPC                       0x141
> @@ -336,6 +355,10 @@
>  #define CSR_HCOUNTEREN                 0x606
>  #define CSR_HGEIE                      0x607
>
> +/* Hypervisor Configuration */
> +#define CSR_HENVCFG                    0x60a
> +#define CSR_HENVCFGH                   0x61a
> +
>  /* Hypervisor Trap Handling (H-extension) */
>  #define CSR_HTVAL                      0x643
>  #define CSR_HIP                                0x644
> @@ -408,6 +431,10 @@
>  #define CSR_MCOUNTEREN                 0x306
>  #define CSR_MSTATUSH                   0x310
>
> +/* Machine Configuration */
> +#define CSR_MENVCFG                    0x30a
> +#define CSR_MENVCFGH                   0x31a
> +
>  /* Machine Trap Handling */
>  #define CSR_MSCRATCH                   0x340
>  #define CSR_MEPC                       0x341
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp@rivosinc.com>

--
Regards,
Atish

[PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs

[Xiang W]

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The latest RISC-V privileged specification introduces xenvcfg CSRs
> to enable/disable certain features/extensions for lower privilege
> modes. This patch adds defines for these new [m|h|s]envcfg CSRs.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>

Regards,
Xiang W
> ---
> ?include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
> ?1 file changed, 27 insertions(+)
> 
> diff --git a/include/sbi/riscv_encoding.h
> b/include/sbi/riscv_encoding.h
> index 574d1c3..c02aa8f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -203,6 +203,22 @@
> ?
> ?#define MHPMEVENT_SSCOF_MASK???????????_ULL(0xFFFF000000000000)
> ?
> +#if __riscv_xlen > 32
> +#define ENVCFG_STCE????????????????????(_ULL(1) << 63)
> +#define ENVCFG_PBMTE???????????????????(_ULL(1) << 62)
> +#else
> +#define ENVCFGH_STCE???????????????????(_UL(1) << 31)
> +#define ENVCFGH_PBMTE??????????????????(_UL(1) << 30)
> +#endif
> +#define ENVCFG_CBZE????????????????????(_UL(1) << 7)
> +#define ENVCFG_CBCFE???????????????????(_UL(1) << 6)
> +#define ENVCFG_CBIE_SHIFT??????????????4
> +#define ENVCFG_CBIE????????????????????(_UL(0x3) <<
> ENVCFG_CBIE_SHIFT)
> +#define ENVCFG_CBIE_ILL????????????????????????_UL(0x0)
> +#define ENVCFG_CBIE_FLUSH??????????????_UL(0x1)
> +#define ENVCFG_CBIE_INV????????????????????????_UL(0x3)
> +#define ENVCFG_FIOM????????????????????_UL(0x1)
> +
> ?/* ===== User-level CSRs ===== */
> ?
> ?/* User Trap Setup (N-extension) */
> @@ -298,6 +314,9 @@
> ?#define CSR_STVEC??????????????????????0x105
> ?#define CSR_SCOUNTEREN?????????????????0x106
> ?
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG????????????????????0x10a
> +
> ?/* Supervisor Trap Handling */
> ?#define CSR_SSCRATCH???????????????????0x140
> ?#define CSR_SEPC???????????????????????0x141
> @@ -336,6 +355,10 @@
> ?#define CSR_HCOUNTEREN?????????????????0x606
> ?#define CSR_HGEIE??????????????????????0x607
> ?
> +/* Hypervisor Configuration */
> +#define CSR_HENVCFG????????????????????0x60a
> +#define CSR_HENVCFGH???????????????????0x61a
> +
> ?/* Hypervisor Trap Handling (H-extension) */
> ?#define CSR_HTVAL??????????????????????0x643
> ?#define CSR_HIP????????????????????????????????0x644
> @@ -408,6 +431,10 @@
> ?#define CSR_MCOUNTEREN?????????????????0x306
> ?#define CSR_MSTATUSH???????????????????0x310
> ?
> +/* Machine Configuration */
> +#define CSR_MENVCFG????????????????????0x30a
> +#define CSR_MENVCFGH???????????????????0x31a
> +
> ?/* Machine Trap Handling */
> ?#define CSR_MSCRATCH???????????????????0x340
> ?#define CSR_MEPC???????????????????????0x341
> -- 
> 2.25.1
> 
> 

[PATCH 1/4] include: Add defines for [m|h|s]envcfg CSRs

[Anup Patel]

On Tue, Mar 29, 2022 at 9:23 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The latest RISC-V privileged specification introduces xenvcfg CSRs
> to enable/disable certain features/extensions for lower privilege
> modes. This patch adds defines for these new [m|h|s]envcfg CSRs.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/riscv_encoding.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index 574d1c3..c02aa8f 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -203,6 +203,22 @@
>
>  #define MHPMEVENT_SSCOF_MASK           _ULL(0xFFFF000000000000)
>
> +#if __riscv_xlen > 32
> +#define ENVCFG_STCE                    (_ULL(1) << 63)
> +#define ENVCFG_PBMTE                   (_ULL(1) << 62)
> +#else
> +#define ENVCFGH_STCE                   (_UL(1) << 31)
> +#define ENVCFGH_PBMTE                  (_UL(1) << 30)
> +#endif
> +#define ENVCFG_CBZE                    (_UL(1) << 7)
> +#define ENVCFG_CBCFE                   (_UL(1) << 6)
> +#define ENVCFG_CBIE_SHIFT              4
> +#define ENVCFG_CBIE                    (_UL(0x3) << ENVCFG_CBIE_SHIFT)
> +#define ENVCFG_CBIE_ILL                        _UL(0x0)
> +#define ENVCFG_CBIE_FLUSH              _UL(0x1)
> +#define ENVCFG_CBIE_INV                        _UL(0x3)
> +#define ENVCFG_FIOM                    _UL(0x1)
> +
>  /* ===== User-level CSRs ===== */
>
>  /* User Trap Setup (N-extension) */
> @@ -298,6 +314,9 @@
>  #define CSR_STVEC                      0x105
>  #define CSR_SCOUNTEREN                 0x106
>
> +/* Supervisor Configuration */
> +#define CSR_SENVCFG                    0x10a
> +
>  /* Supervisor Trap Handling */
>  #define CSR_SSCRATCH                   0x140
>  #define CSR_SEPC                       0x141
> @@ -336,6 +355,10 @@
>  #define CSR_HCOUNTEREN                 0x606
>  #define CSR_HGEIE                      0x607
>
> +/* Hypervisor Configuration */
> +#define CSR_HENVCFG                    0x60a
> +#define CSR_HENVCFGH                   0x61a
> +
>  /* Hypervisor Trap Handling (H-extension) */
>  #define CSR_HTVAL                      0x643
>  #define CSR_HIP                                0x644
> @@ -408,6 +431,10 @@
>  #define CSR_MCOUNTEREN                 0x306
>  #define CSR_MSTATUSH                   0x310
>
> +/* Machine Configuration */
> +#define CSR_MENVCFG                    0x30a
> +#define CSR_MENVCFGH                   0x31a
> +
>  /* Machine Trap Handling */
>  #define CSR_MSCRATCH                   0x340
>  #define CSR_MEPC                       0x341
> --
> 2.25.1
>

[PATCH 2/4] lib: sbi: Detect menvcfg CSR at boot time

[Anup Patel]

From: Atish Patra <atishp@rivosinc.com>

We add the menvcfg CSR as a HART feature and detect it at boot time
using traping mechanism.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 include/sbi/sbi_hart.h | 4 +++-
 lib/sbi/sbi_hart.c     | 9 +++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index a83b45b..57f80bc 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -26,9 +26,11 @@ enum sbi_hart_features {
 	SBI_HART_HAS_TIME = (1 << 4),
 	/** HART has AIA local interrupt CSRs */
 	SBI_HART_HAS_AIA = (1 << 5),
+	/** HART has menvcfg CSR */
+	SBI_HART_HAS_MENVCFG = (1 << 6),
 
 	/** Last index of Hart features*/
-	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_AIA,
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
 };
 
 struct sbi_scratch;
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index e028540..31c8f39 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -304,6 +304,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
 	case SBI_HART_HAS_AIA:
 		fstr = "aia";
 		break;
+	case SBI_HART_HAS_MENVCFG:
+		fstr = "menvcfg";
+		break;
 	default:
 		break;
 	}
@@ -534,6 +537,12 @@ __mhpm_skip:
 		goto __aia_skip;
 	hfeatures->features |= SBI_HART_HAS_AIA;
 __aia_skip:
+
+	/* Detect if hart has menvcfg CSR */
+	csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_MENVCFG;
+
 	return;
 }
 
-- 
2.25.1

[PATCH 2/4] lib: sbi: Detect menvcfg CSR at boot time

[Xiang W]

? 2022-03-29???? 21:22 +0530?Anup Patel???
> From: Atish Patra <atishp@rivosinc.com>
> 
> We add the menvcfg CSR as a HART feature and detect it at boot time
> using traping mechanism.
> 
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>

Regards,
Xiang W
> ---
> ?include/sbi/sbi_hart.h | 4 +++-
> ?lib/sbi/sbi_hart.c???? | 9 +++++++++
> ?2 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index a83b45b..57f80bc 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -26,9 +26,11 @@ enum sbi_hart_features {
> ????????SBI_HART_HAS_TIME = (1 << 4),
> ????????/** HART has AIA local interrupt CSRs */
> ????????SBI_HART_HAS_AIA = (1 << 5),
> +???????/** HART has menvcfg CSR */
> +???????SBI_HART_HAS_MENVCFG = (1 << 6),
> ?
> ????????/** Last index of Hart features*/
> -???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_AIA,
> +???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
> ?};
> ?
> ?struct sbi_scratch;
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index e028540..31c8f39 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -304,6 +304,9 @@ static inline char
> *sbi_hart_feature_id2string(unsigned long feature)
> ????????case SBI_HART_HAS_AIA:
> ????????????????fstr = "aia";
> ????????????????break;
> +???????case SBI_HART_HAS_MENVCFG:
> +???????????????fstr = "menvcfg";
> +???????????????break;
> ????????default:
> ????????????????break;
> ????????}
> @@ -534,6 +537,12 @@ __mhpm_skip:
> ????????????????goto __aia_skip;
> ????????hfeatures->features |= SBI_HART_HAS_AIA;
> ?__aia_skip:
> +
> +???????/* Detect if hart has menvcfg CSR */
> +???????csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
> +???????if (!trap.cause)
> +???????????????hfeatures->features |= SBI_HART_HAS_MENVCFG;
> +
> ????????return;
> ?}
> ?
> -- 
> 2.25.1
> 
> 

[PATCH 2/4] lib: sbi: Detect menvcfg CSR at boot time

[Anup Patel]

On Tue, Mar 29, 2022 at 9:23 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> From: Atish Patra <atishp@rivosinc.com>
>
> We add the menvcfg CSR as a HART feature and detect it at boot time
> using traping mechanism.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/sbi_hart.h | 4 +++-
>  lib/sbi/sbi_hart.c     | 9 +++++++++
>  2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index a83b45b..57f80bc 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -26,9 +26,11 @@ enum sbi_hart_features {
>         SBI_HART_HAS_TIME = (1 << 4),
>         /** HART has AIA local interrupt CSRs */
>         SBI_HART_HAS_AIA = (1 << 5),
> +       /** HART has menvcfg CSR */
> +       SBI_HART_HAS_MENVCFG = (1 << 6),
>
>         /** Last index of Hart features*/
> -       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_AIA,
> +       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
>  };
>
>  struct sbi_scratch;
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index e028540..31c8f39 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -304,6 +304,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
>         case SBI_HART_HAS_AIA:
>                 fstr = "aia";
>                 break;
> +       case SBI_HART_HAS_MENVCFG:
> +               fstr = "menvcfg";
> +               break;
>         default:
>                 break;
>         }
> @@ -534,6 +537,12 @@ __mhpm_skip:
>                 goto __aia_skip;
>         hfeatures->features |= SBI_HART_HAS_AIA;
>  __aia_skip:
> +
> +       /* Detect if hart has menvcfg CSR */
> +       csr_read_allowed(CSR_MENVCFG, (unsigned long)&trap);
> +       if (!trap.cause)
> +               hfeatures->features |= SBI_HART_HAS_MENVCFG;
> +
>         return;
>  }
>
> --
> 2.25.1
>

[PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR

[Anup Patel]

The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
CSR are WARL. We try to enable these bits irrespective whether
these extensions are available or not because writes to these
bits will be ignored if these extensions are not available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 31c8f39..d2c7aba 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
 
 static void mstatus_init(struct sbi_scratch *scratch)
 {
-	unsigned long mstatus_val = 0;
+	unsigned long menvcfg_val, mstatus_val = 0;
 	int cidx;
 	unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 	uint64_t mhpmevent_init_val = 0;
@@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		csr_write_num(CSR_MHPMEVENT3 + cidx, mhpmevent_init_val);
 #endif
 	}
+
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
+		menvcfg_val = csr_read(CSR_MENVCFG);
+
+		/*
+		 * Set menvcfg.CBZE == 1
+		 *
+		 * If Zicboz extension is not available then writes to
+		 * menvcfg.CBZE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBZE;
+
+		/*
+		 * Set menvcfg.CBCFE == 1
+		 *
+		 * If Zicbom extension is not available then writes to
+		 * menvcfg.CBCFE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBCFE;
+
+		/*
+		 * Set menvcfg.CBIE == 3
+		 *
+		 * If Zicbom extension is not available then writes to
+		 * menvcfg.CBIE will be ignored because it is a WARL field.
+		 */
+		menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
+
+		csr_write(CSR_MENVCFG, menvcfg_val);
+	}
+
 	/* Disable all interrupts */
 	csr_write(CSR_MIE, 0);
 
-- 
2.25.1

[PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR

[Atish Patra]

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
> CSR are WARL. We try to enable these bits irrespective whether
> these extensions are available or not because writes to these
> bits will be ignored if these extensions are not available.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 31c8f39..d2c7aba 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
>
>  static void mstatus_init(struct sbi_scratch *scratch)
>  {
> -       unsigned long mstatus_val = 0;
> +       unsigned long menvcfg_val, mstatus_val = 0;
>         int cidx;
>         unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
>         uint64_t mhpmevent_init_val = 0;
> @@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                 csr_write_num(CSR_MHPMEVENT3 + cidx, mhpmevent_init_val);
>  #endif
>         }
> +
> +       if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> +               menvcfg_val = csr_read(CSR_MENVCFG);
> +
> +               /*
> +                * Set menvcfg.CBZE == 1
> +                *
> +                * If Zicboz extension is not available then writes to
> +                * menvcfg.CBZE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBZE;
> +
> +               /*
> +                * Set menvcfg.CBCFE == 1
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBCFE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBCFE;
> +
> +               /*
> +                * Set menvcfg.CBIE == 3
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBIE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> +
> +               csr_write(CSR_MENVCFG, menvcfg_val);
> +       }
> +
>         /* Disable all interrupts */
>         csr_write(CSR_MIE, 0);
>
> --
> 2.25.1
>


Reviewed-by: Atish Patra <atishp@rivosinc.com>

--
Regards,
Atish

[PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR

[Xiang W]

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
> CSR are WARL. We try to enable these bits irrespective whether
> these extensions are available or not because writes to these
> bits will be ignored if these extensions are not available.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>

Regards,
Xiang W
> ---
> ?lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
> ?1 file changed, 32 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 31c8f39..d2c7aba 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
> ?
> ?static void mstatus_init(struct sbi_scratch *scratch)
> ?{
> -???????unsigned long mstatus_val = 0;
> +???????unsigned long menvcfg_val, mstatus_val = 0;
> ????????int cidx;
> ????????unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
> ????????uint64_t mhpmevent_init_val = 0;
> @@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ????????????????csr_write_num(CSR_MHPMEVENT3 + cidx,
> mhpmevent_init_val);
> ?#endif
> ????????}
> +
> +???????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> +???????????????menvcfg_val = csr_read(CSR_MENVCFG);
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBZE == 1
> +??????????????? *
> +??????????????? * If Zicboz extension is not available then writes to
> +??????????????? * menvcfg.CBZE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBZE;
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBCFE == 1
> +??????????????? *
> +??????????????? * If Zicbom extension is not available then writes to
> +??????????????? * menvcfg.CBCFE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBCFE;
> +
> +???????????????/*
> +??????????????? * Set menvcfg.CBIE == 3
> +??????????????? *
> +??????????????? * If Zicbom extension is not available then writes to
> +??????????????? * menvcfg.CBIE will be ignored because it is a WARL
> field.
> +??????????????? */
> +???????????????menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> +
> +???????????????csr_write(CSR_MENVCFG, menvcfg_val);
> +???????}
> +
> ????????/* Disable all interrupts */
> ????????csr_write(CSR_MIE, 0);
> ?
> -- 
> 2.25.1
> 
> 

[PATCH 3/4] lib: sbi: Enable Zicbo[m|z] extensions in the menvcfg CSR

[Anup Patel]

On Tue, Mar 29, 2022 at 9:23 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The bits to configure/enable Zicbo[m|z] extensions in the menvcfg
> CSR are WARL. We try to enable these bits irrespective whether
> these extensions are available or not because writes to these
> bits will be ignored if these extensions are not available.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_hart.c | 33 ++++++++++++++++++++++++++++++++-
>  1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 31c8f39..d2c7aba 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -39,7 +39,7 @@ static unsigned long hart_features_offset;
>
>  static void mstatus_init(struct sbi_scratch *scratch)
>  {
> -       unsigned long mstatus_val = 0;
> +       unsigned long menvcfg_val, mstatus_val = 0;
>         int cidx;
>         unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
>         uint64_t mhpmevent_init_val = 0;
> @@ -86,6 +86,37 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                 csr_write_num(CSR_MHPMEVENT3 + cidx, mhpmevent_init_val);
>  #endif
>         }
> +
> +       if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> +               menvcfg_val = csr_read(CSR_MENVCFG);
> +
> +               /*
> +                * Set menvcfg.CBZE == 1
> +                *
> +                * If Zicboz extension is not available then writes to
> +                * menvcfg.CBZE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBZE;
> +
> +               /*
> +                * Set menvcfg.CBCFE == 1
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBCFE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBCFE;
> +
> +               /*
> +                * Set menvcfg.CBIE == 3
> +                *
> +                * If Zicbom extension is not available then writes to
> +                * menvcfg.CBIE will be ignored because it is a WARL field.
> +                */
> +               menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> +
> +               csr_write(CSR_MENVCFG, menvcfg_val);
> +       }
> +
>         /* Disable all interrupts */
>         csr_write(CSR_MIE, 0);
>
> --
> 2.25.1
>

[PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR

[Anup Patel]

The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
available so we try to enable menvcfg.PBMTE bit irrespective whether
Svpbmt is available or not.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index d2c7aba..6be9286 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		 */
 		menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
 
+		/*
+		 * Set menvcfg.PBMTE == 1 for RV64 or RV128
+		 *
+		 * If Svpbmt extension is not available then menvcfg.PBMTE
+		 * will be read-only zero.
+		 */
+#if __riscv_xlen > 32
+		menvcfg_val |= ENVCFG_PBMTE;
+#endif
+
 		csr_write(CSR_MENVCFG, menvcfg_val);
 	}
 
-- 
2.25.1

[PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR

[Atish Patra]

On Tue, Mar 29, 2022 at 8:53 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
> available so we try to enable menvcfg.PBMTE bit irrespective whether
> Svpbmt is available or not.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  lib/sbi/sbi_hart.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d2c7aba..6be9286 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                  */
>                 menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
>
> +               /*
> +                * Set menvcfg.PBMTE == 1 for RV64 or RV128
> +                *
> +                * If Svpbmt extension is not available then menvcfg.PBMTE
> +                * will be read-only zero.
> +                */
> +#if __riscv_xlen > 32
> +               menvcfg_val |= ENVCFG_PBMTE;
> +#endif
> +
>                 csr_write(CSR_MENVCFG, menvcfg_val);
>         }
>
> --
> 2.25.1
>

Reviewed-by: Atish Patra <atishp@rivosinc.com>
-- 
Regards,
Atish

[PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR

[Xiang W]

? 2022-03-29???? 21:22 +0530?Anup Patel???
> The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
> available so we try to enable menvcfg.PBMTE bit irrespective whether
> Svpbmt is available or not.
> 
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Xiang W <wxjstz@126.com>

Regards,
Xiang W
> ---
> ?lib/sbi/sbi_hart.c | 10 ++++++++++
> ?1 file changed, 10 insertions(+)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d2c7aba..6be9286 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ???????????????? */
> ????????????????menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
> ?
> +???????????????/*
> +??????????????? * Set menvcfg.PBMTE == 1 for RV64 or RV128
> +??????????????? *
> +??????????????? * If Svpbmt extension is not available then
> menvcfg.PBMTE
> +??????????????? * will be read-only zero.
> +??????????????? */
> +#if __riscv_xlen > 32
> +???????????????menvcfg_val |= ENVCFG_PBMTE;
> +#endif
> +
> ????????????????csr_write(CSR_MENVCFG, menvcfg_val);
> ????????}
> ?
> -- 
> 2.25.1
> 
> 

[PATCH 4/4] lib: sbi: Enable Svpbmt extension in the menvcfg CSR

[Anup Patel]

On Tue, Mar 29, 2022 at 9:23 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The menvcfg.PBMTE bit is read-only zero when Svpbmt extension is not
> available so we try to enable menvcfg.PBMTE bit irrespective whether
> Svpbmt is available or not.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_hart.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index d2c7aba..6be9286 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -114,6 +114,16 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                  */
>                 menvcfg_val |= ENVCFG_CBIE_INV << ENVCFG_CBIE_SHIFT;
>
> +               /*
> +                * Set menvcfg.PBMTE == 1 for RV64 or RV128
> +                *
> +                * If Svpbmt extension is not available then menvcfg.PBMTE
> +                * will be read-only zero.
> +                */
> +#if __riscv_xlen > 32
> +               menvcfg_val |= ENVCFG_PBMTE;
> +#endif
> +
>                 csr_write(CSR_MENVCFG, menvcfg_val);
>         }
>
> --
> 2.25.1
>