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From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 0/3] QEMU RISC-V priv spec version fixes
Date: Fri, 29 Apr 2022 21:04:28 +0530	[thread overview]
Message-ID: <20220429153431.308829-1-apatel@ventanamicro.com> (raw)

This series covers few fixes discovered while trying to detect priv spec
version on QEMU virt machine and QEMU sifive_u machine.

These patches can also be found in riscv_priv_version_fixes_v1 branch at:
https://github.com/avpatel/qemu.git

Anup Patel (3):
  target/riscv: Don't force update priv spec version to latest
  target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or
    higher
  target/riscv: Consider priv spec version when generating ISA string

 target/riscv/cpu.c      | 46 ++++++++++++++++++++++-------------------
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      |  2 ++
 3 files changed, 30 insertions(+), 21 deletions(-)

-- 
2.34.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Anup Patel <apatel@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Atish Patra <atishp@atishpatra.org>
Subject: [PATCH 0/3] QEMU RISC-V priv spec version fixes
Date: Fri, 29 Apr 2022 21:04:28 +0530	[thread overview]
Message-ID: <20220429153431.308829-1-apatel@ventanamicro.com> (raw)

This series covers few fixes discovered while trying to detect priv spec
version on QEMU virt machine and QEMU sifive_u machine.

These patches can also be found in riscv_priv_version_fixes_v1 branch at:
https://github.com/avpatel/qemu.git

Anup Patel (3):
  target/riscv: Don't force update priv spec version to latest
  target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or
    higher
  target/riscv: Consider priv spec version when generating ISA string

 target/riscv/cpu.c      | 46 ++++++++++++++++++++++-------------------
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      |  2 ++
 3 files changed, 30 insertions(+), 21 deletions(-)

-- 
2.34.1



             reply	other threads:[~2022-04-29 15:35 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-29 15:34 Anup Patel [this message]
2022-04-29 15:34 ` [PATCH 0/3] QEMU RISC-V priv spec version fixes Anup Patel
2022-04-29 15:34 ` [PATCH 1/3] target/riscv: Don't force update priv spec version to latest Anup Patel
2022-04-29 15:34   ` Anup Patel
2022-04-30  2:57   ` Frank Chang
2022-04-30  2:57     ` Frank Chang
2022-05-04  9:13   ` Alistair Francis
2022-05-09 20:02   ` Atish Patra
2022-04-29 15:34 ` [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Anup Patel
2022-04-29 15:34   ` Anup Patel
2022-04-30  3:13   ` Frank Chang
2022-04-30  3:13     ` Frank Chang
2022-05-04  9:14   ` Alistair Francis
2022-05-04  9:53   ` Frank Chang
2022-05-09 19:54     ` Atish Patra
2022-04-29 15:34 ` [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string Anup Patel
2022-04-29 15:34   ` Anup Patel
2022-04-30  3:09   ` Frank Chang
2022-04-30  3:09     ` Frank Chang
2022-04-30  4:29     ` Anup Patel
2022-04-30  4:29       ` Anup Patel
2022-04-30  5:33       ` Frank Chang
2022-04-30  5:33         ` Frank Chang
2022-05-04  9:59       ` Alistair Francis

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