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From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string
Date: Fri, 29 Apr 2022 21:04:31 +0530	[thread overview]
Message-ID: <20220429153431.308829-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220429153431.308829-1-apatel@ventanamicro.com>

Most of the multi-letter extensions (such as Svpbmt, Svnapot, Svinval,
etc) are only available after Priv spec v1.12 so ISA string generation
should check the minimum required priv spec version for all extensions.

Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
device tree")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 target/riscv/cpu.c | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02ee7d45d8..d8c88b96bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -44,6 +44,7 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 struct isa_ext_data {
     const char *name;
     bool enabled;
+    uint32_t min_priv_ver;
 };
 
 const char * const riscv_int_regnames[] = {
@@ -974,7 +975,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_props(dc, riscv_cpu_properties);
 }
 
-#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
+#define ISA_EDATA_ENTRY(name, prop, priv) {#name, cpu->cfg.prop, priv}
 
 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
 {
@@ -1000,25 +1001,26 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
      *    extensions by an underscore.
      */
     struct isa_ext_data isa_edata_arr[] = {
-        ISA_EDATA_ENTRY(zfh, ext_zfh),
-        ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
-        ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
-        ISA_EDATA_ENTRY(zdinx, ext_zdinx),
-        ISA_EDATA_ENTRY(zba, ext_zba),
-        ISA_EDATA_ENTRY(zbb, ext_zbb),
-        ISA_EDATA_ENTRY(zbc, ext_zbc),
-        ISA_EDATA_ENTRY(zbs, ext_zbs),
-        ISA_EDATA_ENTRY(zve32f, ext_zve32f),
-        ISA_EDATA_ENTRY(zve64f, ext_zve64f),
-        ISA_EDATA_ENTRY(svinval, ext_svinval),
-        ISA_EDATA_ENTRY(svnapot, ext_svnapot),
-        ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+        ISA_EDATA_ENTRY(zfh, ext_zfh, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zfhmin, ext_zfhmin, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zfinx, ext_zfinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zhinx, ext_zhinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zdinx, ext_zdinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zba, ext_zba, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbb, ext_zbb, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbc, ext_zbc, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbs, ext_zbs, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zve32f, ext_zve32f, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zve64f, ext_zve64f, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svinval, ext_svinval, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svnapot, ext_svnapot, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svpbmt, ext_svpbmt, PRIV_VERSION_1_12_0),
     };
 
     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_edata_arr[i].enabled) {
+        if (isa_edata_arr[i].enabled &&
+            cpu->env.priv_ver >= isa_edata_arr[i].min_priv_ver) {
             new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
             g_free(old);
             old = new;
-- 
2.34.1



WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Anup Patel <apatel@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Atish Patra <atishp@atishpatra.org>
Subject: [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string
Date: Fri, 29 Apr 2022 21:04:31 +0530	[thread overview]
Message-ID: <20220429153431.308829-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220429153431.308829-1-apatel@ventanamicro.com>

Most of the multi-letter extensions (such as Svpbmt, Svnapot, Svinval,
etc) are only available after Priv spec v1.12 so ISA string generation
should check the minimum required priv spec version for all extensions.

Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
device tree")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 target/riscv/cpu.c | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02ee7d45d8..d8c88b96bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -44,6 +44,7 @@ static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
 struct isa_ext_data {
     const char *name;
     bool enabled;
+    uint32_t min_priv_ver;
 };
 
 const char * const riscv_int_regnames[] = {
@@ -974,7 +975,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_props(dc, riscv_cpu_properties);
 }
 
-#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop}
+#define ISA_EDATA_ENTRY(name, prop, priv) {#name, cpu->cfg.prop, priv}
 
 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
 {
@@ -1000,25 +1001,26 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
      *    extensions by an underscore.
      */
     struct isa_ext_data isa_edata_arr[] = {
-        ISA_EDATA_ENTRY(zfh, ext_zfh),
-        ISA_EDATA_ENTRY(zfhmin, ext_zfhmin),
-        ISA_EDATA_ENTRY(zfinx, ext_zfinx),
-        ISA_EDATA_ENTRY(zhinx, ext_zhinx),
-        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin),
-        ISA_EDATA_ENTRY(zdinx, ext_zdinx),
-        ISA_EDATA_ENTRY(zba, ext_zba),
-        ISA_EDATA_ENTRY(zbb, ext_zbb),
-        ISA_EDATA_ENTRY(zbc, ext_zbc),
-        ISA_EDATA_ENTRY(zbs, ext_zbs),
-        ISA_EDATA_ENTRY(zve32f, ext_zve32f),
-        ISA_EDATA_ENTRY(zve64f, ext_zve64f),
-        ISA_EDATA_ENTRY(svinval, ext_svinval),
-        ISA_EDATA_ENTRY(svnapot, ext_svnapot),
-        ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
+        ISA_EDATA_ENTRY(zfh, ext_zfh, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zfhmin, ext_zfhmin, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zfinx, ext_zfinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zhinx, ext_zhinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zdinx, ext_zdinx, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zba, ext_zba, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbb, ext_zbb, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbc, ext_zbc, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zbs, ext_zbs, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zve32f, ext_zve32f, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(zve64f, ext_zve64f, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svinval, ext_svinval, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svnapot, ext_svnapot, PRIV_VERSION_1_12_0),
+        ISA_EDATA_ENTRY(svpbmt, ext_svpbmt, PRIV_VERSION_1_12_0),
     };
 
     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
-        if (isa_edata_arr[i].enabled) {
+        if (isa_edata_arr[i].enabled &&
+            cpu->env.priv_ver >= isa_edata_arr[i].min_priv_ver) {
             new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
             g_free(old);
             old = new;
-- 
2.34.1



  parent reply	other threads:[~2022-04-29 15:35 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-29 15:34 [PATCH 0/3] QEMU RISC-V priv spec version fixes Anup Patel
2022-04-29 15:34 ` Anup Patel
2022-04-29 15:34 ` [PATCH 1/3] target/riscv: Don't force update priv spec version to latest Anup Patel
2022-04-29 15:34   ` Anup Patel
2022-04-30  2:57   ` Frank Chang
2022-04-30  2:57     ` Frank Chang
2022-05-04  9:13   ` Alistair Francis
2022-05-09 20:02   ` Atish Patra
2022-04-29 15:34 ` [PATCH 2/3] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Anup Patel
2022-04-29 15:34   ` Anup Patel
2022-04-30  3:13   ` Frank Chang
2022-04-30  3:13     ` Frank Chang
2022-05-04  9:14   ` Alistair Francis
2022-05-04  9:53   ` Frank Chang
2022-05-09 19:54     ` Atish Patra
2022-04-29 15:34 ` Anup Patel [this message]
2022-04-29 15:34   ` [PATCH 3/3] target/riscv: Consider priv spec version when generating ISA string Anup Patel
2022-04-30  3:09   ` Frank Chang
2022-04-30  3:09     ` Frank Chang
2022-04-30  4:29     ` Anup Patel
2022-04-30  4:29       ` Anup Patel
2022-04-30  5:33       ` Frank Chang
2022-04-30  5:33         ` Frank Chang
2022-05-04  9:59       ` Alistair Francis

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