* [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-24 16:02 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Bhadram Varka
` (7 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding, Bhadram Varka
From: Thierry Reding <treding@nvidia.com>
Add the clocks and resets used by the MGBE Ethernet hardware found on
Tegra234 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++
include/dt-bindings/reset/tegra234-reset.h | 8 ++
2 files changed, 109 insertions(+)
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index bd4c3086a2da..bab85d9ba8cd 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -164,10 +164,111 @@
#define TEGRA234_CLK_PEX1_C5_CORE 225U
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
#define TEGRA234_CLK_PLLC4 237U
+/** @brief RX clock recovered from MGBE0 lane input */
+#define TEGRA234_CLK_MGBE0_RX_INPUT 248U
+/** @brief RX clock recovered from MGBE1 lane input */
+#define TEGRA234_CLK_MGBE1_RX_INPUT 249U
+/** @brief RX clock recovered from MGBE2 lane input */
+#define TEGRA234_CLK_MGBE2_RX_INPUT 250U
+/** @brief RX clock recovered from MGBE3 lane input */
+#define TEGRA234_CLK_MGBE3_RX_INPUT 251U
/** @brief 32K input clock provided by PMIC */
#define TEGRA234_CLK_CLK_32K 289U
+/** @brief Monitored branch of MBGE0 RX input clock */
+#define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U
+/** @brief Monitored branch of MBGE1 RX input clock */
+#define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U
+/** @brief Monitored branch of MBGE2 RX input clock */
+#define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U
+/** @brief Monitored branch of MBGE3 RX input clock */
+#define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U
+/** @brief Monitored branch of MGBE0 RX PCS mux output */
+#define TEGRA234_CLK_MGBE0_RX_PCS_M 361U
+/** @brief Monitored branch of MGBE1 RX PCS mux output */
+#define TEGRA234_CLK_MGBE1_RX_PCS_M 362U
+/** @brief Monitored branch of MGBE2 RX PCS mux output */
+#define TEGRA234_CLK_MGBE2_RX_PCS_M 363U
+/** @brief Monitored branch of MGBE3 RX PCS mux output */
+#define TEGRA234_CLK_MGBE3_RX_PCS_M 364U
+/** @brief RX PCS clock recovered from MGBE0 lane input */
+#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U
+/** @brief RX PCS clock recovered from MGBE1 lane input */
+#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U
+/** @brief RX PCS clock recovered from MGBE2 lane input */
+#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U
+/** @brief RX PCS clock recovered from MGBE3 lane input */
+#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U
+/** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE0_RX_PCS 373U
+/** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_TX 374U
+/** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_TX_PCS 375U
+/** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U
+/** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE0_MAC 377U
+/** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */
+#define TEGRA234_CLK_MGBE0_MACSEC 378U
+/** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE0_EEE_PCS 379U
+/** @brief GBE_UPHY_MGBE0_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE0_APP 380U
+/** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE0_PTP_REF 381U
+/** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE1_RX_PCS 382U
+/** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_TX 383U
+/** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_TX_PCS 384U
+/** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U
+/** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE1_MAC 386U
+/** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE1_EEE_PCS 388U
+/** @brief GBE_UPHY_MGBE1_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE1_APP 389U
+/** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE1_PTP_REF 390U
+/** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE2_RX_PCS 391U
+/** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_TX 392U
+/** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_TX_PCS 393U
+/** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U
+/** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE2_MAC 395U
+/** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE2_EEE_PCS 397U
+/** @brief GBE_UPHY_MGBE2_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE2_APP 398U
+/** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE2_PTP_REF 399U
+/** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */
+#define TEGRA234_CLK_MGBE3_RX_PCS 400U
+/** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_TX 401U
+/** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_TX_PCS 402U
+/** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */
+#define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U
+/** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */
+#define TEGRA234_CLK_MGBE3_MAC 404U
+/** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */
+#define TEGRA234_CLK_MGBE3_MACSEC 405U
+/** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */
+#define TEGRA234_CLK_MGBE3_EEE_PCS 406U
+/** @brief GBE_UPHY_MGBE3_APP_CLK gate output */
+#define TEGRA234_CLK_MGBE3_APP 407U
+/** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */
+#define TEGRA234_CLK_MGBE3_PTP_REF 408U
/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
#define TEGRA234_CLK_AZA_2XBIT 457U
/** @brief aza_2xbitclk / 2 (aza_bitclk) */
#define TEGRA234_CLK_AZA_BIT 458U
+
#endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 547ca3b60caa..55e397823a38 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -29,6 +29,12 @@
#define TEGRA234_RESET_I2C7 33U
#define TEGRA234_RESET_I2C8 34U
#define TEGRA234_RESET_I2C9 35U
+#define TEGRA234_RESET_MGBE0_PCS 45U
+#define TEGRA234_RESET_MGBE0_MAC 46U
+#define TEGRA234_RESET_MGBE1_PCS 49U
+#define TEGRA234_RESET_MGBE1_MAC 50U
+#define TEGRA234_RESET_MGBE2_PCS 53U
+#define TEGRA234_RESET_MGBE2_MAC 54U
#define TEGRA234_RESET_PEX2_CORE_10 56U
#define TEGRA234_RESET_PEX2_CORE_10_APB 57U
#define TEGRA234_RESET_PEX2_COMMON_APB 58U
@@ -43,6 +49,8 @@
#define TEGRA234_RESET_QSPI0 76U
#define TEGRA234_RESET_QSPI1 77U
#define TEGRA234_RESET_SDMMC4 85U
+#define TEGRA234_RESET_MGBE3_PCS 87U
+#define TEGRA234_RESET_MGBE3_MAC 88U
#define TEGRA234_RESET_UARTA 100U
#define TEGRA234_RESET_PEX0_CORE_0 116U
#define TEGRA234_RESET_PEX0_CORE_1 117U
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets
2022-06-23 7:46 ` [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Bhadram Varka
@ 2022-06-24 16:02 ` Krzysztof Kozlowski
2022-06-24 16:21 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 16:02 UTC (permalink / raw)
To: Bhadram Varka, netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding
On 23/06/2022 09:46, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the clocks and resets used by the MGBE Ethernet hardware found on
> Tegra234 SoCs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> ---
> include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++
> include/dt-bindings/reset/tegra234-reset.h | 8 ++
> 2 files changed, 109 insertions(+)
>
> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
> index bd4c3086a2da..bab85d9ba8cd 100644
> --- a/include/dt-bindings/clock/tegra234-clock.h
> +++ b/include/dt-bindings/clock/tegra234-clock.h
> @@ -164,10 +164,111 @@
> #define TEGRA234_CLK_PEX1_C5_CORE 225U
> /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
> #define TEGRA234_CLK_PLLC4 237U
> +/** @brief RX clock recovered from MGBE0 lane input */
The IDs should be abstract integer incremented by one, without any
holes. I guess the issue was here before, so it's fine but I'll start
complaining at some point :)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets
2022-06-24 16:02 ` Krzysztof Kozlowski
@ 2022-06-24 16:21 ` Thierry Reding
2022-06-24 17:12 ` Krzysztof Kozlowski
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2022-06-24 16:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bhadram Varka, netdev, devicetree, linux-tegra, robh+dt,
krzysztof.kozlowski+dt, jonathanh, kuba, catalin.marinas, will,
Thierry Reding
[-- Attachment #1: Type: text/plain, Size: 1606 bytes --]
On Fri, Jun 24, 2022 at 06:02:58PM +0200, Krzysztof Kozlowski wrote:
> On 23/06/2022 09:46, Bhadram Varka wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Add the clocks and resets used by the MGBE Ethernet hardware found on
> > Tegra234 SoCs.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> > ---
> > include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++
> > include/dt-bindings/reset/tegra234-reset.h | 8 ++
> > 2 files changed, 109 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
> > index bd4c3086a2da..bab85d9ba8cd 100644
> > --- a/include/dt-bindings/clock/tegra234-clock.h
> > +++ b/include/dt-bindings/clock/tegra234-clock.h
> > @@ -164,10 +164,111 @@
> > #define TEGRA234_CLK_PEX1_C5_CORE 225U
> > /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
> > #define TEGRA234_CLK_PLLC4 237U
> > +/** @brief RX clock recovered from MGBE0 lane input */
>
> The IDs should be abstract integer incremented by one, without any
> holes. I guess the issue was here before, so it's fine but I'll start
> complaining at some point :)
These IDs originate from firmware and therefore are more like hardware
IDs rather than an arbitrary enumeration. These will be used directly in
IPC calls with the firmware to reference individual clocks and resets.
We've adopted these 1:1 in order to avoid adding an extra level of
indirection (via some lookup table) in the kernel.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets
2022-06-24 16:21 ` Thierry Reding
@ 2022-06-24 17:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 17:12 UTC (permalink / raw)
To: Thierry Reding
Cc: Bhadram Varka, netdev, devicetree, linux-tegra, robh+dt,
krzysztof.kozlowski+dt, jonathanh, kuba, catalin.marinas, will,
Thierry Reding
On 24/06/2022 18:21, Thierry Reding wrote:
> On Fri, Jun 24, 2022 at 06:02:58PM +0200, Krzysztof Kozlowski wrote:
>> On 23/06/2022 09:46, Bhadram Varka wrote:
>>> From: Thierry Reding <treding@nvidia.com>
>>>
>>> Add the clocks and resets used by the MGBE Ethernet hardware found on
>>> Tegra234 SoCs.
>>>
>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
>>> ---
>>> include/dt-bindings/clock/tegra234-clock.h | 101 +++++++++++++++++++++
>>> include/dt-bindings/reset/tegra234-reset.h | 8 ++
>>> 2 files changed, 109 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
>>> index bd4c3086a2da..bab85d9ba8cd 100644
>>> --- a/include/dt-bindings/clock/tegra234-clock.h
>>> +++ b/include/dt-bindings/clock/tegra234-clock.h
>>> @@ -164,10 +164,111 @@
>>> #define TEGRA234_CLK_PEX1_C5_CORE 225U
>>> /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
>>> #define TEGRA234_CLK_PLLC4 237U
>>> +/** @brief RX clock recovered from MGBE0 lane input */
>>
>> The IDs should be abstract integer incremented by one, without any
>> holes. I guess the issue was here before, so it's fine but I'll start
>> complaining at some point :)
>
> These IDs originate from firmware and therefore are more like hardware
> IDs rather than an arbitrary enumeration. These will be used directly in
> IPC calls with the firmware to reference individual clocks and resets.
If they are actually shared with firmware, it's fine. Thanks for
explanation.
> We've adopted these 1:1 in order to avoid adding an extra level of
> indirection (via some lookup table) in the kernel.
This if fine, but some folks (including myself once...) define in
bindings register values and offsets without any actual need. I was
afraid that's the case here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
2022-06-25 20:18 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Bhadram Varka
` (6 subsequent siblings)
8 siblings, 2 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding, Bhadram Varka
From: Thierry Reding <treding@nvidia.com>
Add the memory client and stream ID definitions for the MGBE hardware
found on Tegra234 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
include/dt-bindings/memory/tegra234-mc.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index e3b0e9da295d..8b0ddcb715ff 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -11,11 +11,16 @@
/* NISO0 stream IDs */
#define TEGRA234_SID_APE 0x02
#define TEGRA234_SID_HDA 0x03
+#define TEGRA234_SID_GPCDMA 0x04
+#define TEGRA234_SID_MGBE 0x06
#define TEGRA234_SID_PCIE0 0x12
#define TEGRA234_SID_PCIE4 0x13
#define TEGRA234_SID_PCIE5 0x14
#define TEGRA234_SID_PCIE6 0x15
#define TEGRA234_SID_PCIE9 0x1f
+#define TEGRA234_SID_MGBE_VF1 0x49
+#define TEGRA234_SID_MGBE_VF2 0x4a
+#define TEGRA234_SID_MGBE_VF3 0x4b
/* NISO1 stream IDs */
#define TEGRA234_SID_SDMMC4 0x02
@@ -61,8 +66,24 @@
#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48
/* PCIE7r1 read clients */
#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49
+/* MGBE0 read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEARD 0x58
+/* MGBEB read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEBRD 0x59
+/* MGBEC read client */
+#define TEGRA234_MEMORY_CLIENT_MGBECRD 0x5a
+/* MGBED read client */
+#define TEGRA234_MEMORY_CLIENT_MGBEDRD 0x5b
+/* MGBE0 write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEAWR 0x5c
+/* MGBEB write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEBWR 0x5f
+/* MGBEC write client */
+#define TEGRA234_MEMORY_CLIENT_MGBECWR 0x61
/* sdmmcd memory read client */
#define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
+/* MGBED write client */
+#define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
/* sdmmcd memory write client */
#define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
/* BPMP read client */
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: (subset) [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-06-23 7:46 ` [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Bhadram Varka
@ 2022-06-24 16:06 ` Krzysztof Kozlowski
2022-06-24 16:10 ` Krzysztof Kozlowski
2022-06-25 20:18 ` Krzysztof Kozlowski
1 sibling, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 16:06 UTC (permalink / raw)
To: linux-tegra, netdev, devicetree, vbhadram
Cc: Krzysztof Kozlowski, thierry.reding, treding, robh+dt,
catalin.marinas, krzysztof.kozlowski+dt, kuba, jonathanh, will
On Thu, 23 Jun 2022 13:16:09 +0530, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the memory client and stream ID definitions for the MGBE hardware
> found on Tegra234 SoCs.
>
>
Applied, thanks!
[3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
https://git.kernel.org/krzk/linux-mem-ctrl/c/f35756b5fc488912b8bc5f5686e4f236d00923d7
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: (subset) [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
@ 2022-06-24 16:10 ` Krzysztof Kozlowski
2022-06-24 16:19 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 16:10 UTC (permalink / raw)
To: linux-tegra, netdev, devicetree, vbhadram
Cc: thierry.reding, treding, robh+dt, catalin.marinas,
krzysztof.kozlowski+dt, kuba, jonathanh, will
On 24/06/2022 18:06, Krzysztof Kozlowski wrote:
> On Thu, 23 Jun 2022 13:16:09 +0530, Bhadram Varka wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> Add the memory client and stream ID definitions for the MGBE hardware
>> found on Tegra234 SoCs.
>>
>>
>
> Applied, thanks!
>
> [3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
> https://git.kernel.org/krzk/linux-mem-ctrl/c/f35756b5fc488912b8bc5f5686e4f236d00923d7
>
Hmm, actually now I think you might need it for DTS, although there was
no cover letter here explaining merging/dependencies...
I could provide you a tag with it or opposite (take a tag with only the
header).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: (subset) [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-06-24 16:10 ` Krzysztof Kozlowski
@ 2022-06-24 16:19 ` Thierry Reding
0 siblings, 0 replies; 25+ messages in thread
From: Thierry Reding @ 2022-06-24 16:19 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-tegra, netdev, devicetree, vbhadram, treding, robh+dt,
catalin.marinas, krzysztof.kozlowski+dt, kuba, jonathanh, will
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On Fri, Jun 24, 2022 at 06:10:54PM +0200, Krzysztof Kozlowski wrote:
> On 24/06/2022 18:06, Krzysztof Kozlowski wrote:
> > On Thu, 23 Jun 2022 13:16:09 +0530, Bhadram Varka wrote:
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> Add the memory client and stream ID definitions for the MGBE hardware
> >> found on Tegra234 SoCs.
> >>
> >>
> >
> > Applied, thanks!
> >
> > [3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
> > https://git.kernel.org/krzk/linux-mem-ctrl/c/f35756b5fc488912b8bc5f5686e4f236d00923d7
> >
>
> Hmm, actually now I think you might need it for DTS, although there was
> no cover letter here explaining merging/dependencies...
>
> I could provide you a tag with it or opposite (take a tag with only the
> header).
I can pick this up into the Tegra tree where I already carry an earlier
patch for Tegra234 GPCDMA that you had acked. That works better for this
model since, as you said, this is needed as a dependency for the DTS
files.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients
2022-06-23 7:46 ` [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
@ 2022-06-25 20:18 ` Krzysztof Kozlowski
1 sibling, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-25 20:18 UTC (permalink / raw)
To: Bhadram Varka, netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding
On 23/06/2022 09:46, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add the memory client and stream ID definitions for the MGBE hardware
> found on Tegra234 SoCs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Dropped from my tree.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 2/9] dt-bindings: Add Tegra234 MGBE clocks and resets Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 3/9] dt-bindings: memory: Add Tegra234 MGBE memory clients Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
2022-06-25 20:18 ` Krzysztof Kozlowski
2022-06-23 7:46 ` [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE Bhadram Varka
` (5 subsequent siblings)
8 siblings, 2 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding, Bhadram Varka
From: Thierry Reding <treding@nvidia.com>
Tegra234 has multiple network interfaces with each their own memory
clients and stream IDs to allow for proper isolation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index e23ebd421f17..a9e8fd99730f 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -11,6 +11,76 @@
static const struct tegra_mc_client tegra234_mc_clients[] = {
{
+ .id = TEGRA234_MEMORY_CLIENT_MGBEARD,
+ .name = "mgbeard",
+ .sid = TEGRA234_SID_MGBE,
+ .regs = {
+ .sid = {
+ .override = 0x2c0,
+ .security = 0x2c4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
+ .name = "mgbebrd",
+ .sid = TEGRA234_SID_MGBE_VF1,
+ .regs = {
+ .sid = {
+ .override = 0x2c8,
+ .security = 0x2cc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBECRD,
+ .name = "mgbecrd",
+ .sid = TEGRA234_SID_MGBE_VF2,
+ .regs = {
+ .sid = {
+ .override = 0x2d0,
+ .security = 0x2d4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
+ .name = "mgbedrd",
+ .sid = TEGRA234_SID_MGBE_VF3,
+ .regs = {
+ .sid = {
+ .override = 0x2d8,
+ .security = 0x2dc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
+ .name = "mgbeawr",
+ .sid = TEGRA234_SID_MGBE,
+ .regs = {
+ .sid = {
+ .override = 0x2e0,
+ .security = 0x2e4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
+ .name = "mgbebwr",
+ .sid = TEGRA234_SID_MGBE_VF1,
+ .regs = {
+ .sid = {
+ .override = 0x2f8,
+ .security = 0x2fc,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBECWR,
+ .name = "mgbecwr",
+ .sid = TEGRA234_SID_MGBE_VF2,
+ .regs = {
+ .sid = {
+ .override = 0x308,
+ .security = 0x30c,
+ },
+ },
+ }, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
.name = "sdmmcrab",
.sid = TEGRA234_SID_SDMMC4,
@@ -20,6 +90,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x31c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
+ .name = "mgbedwr",
+ .sid = TEGRA234_SID_MGBE_VF3,
+ .regs = {
+ .sid = {
+ .override = 0x328,
+ .security = 0x32c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
.name = "sdmmcwab",
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: (subset) [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-06-23 7:46 ` [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Bhadram Varka
@ 2022-06-24 16:06 ` Krzysztof Kozlowski
2022-06-24 16:24 ` Thierry Reding
2022-06-25 20:18 ` Krzysztof Kozlowski
1 sibling, 1 reply; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 16:06 UTC (permalink / raw)
To: linux-tegra, netdev, devicetree, vbhadram
Cc: Krzysztof Kozlowski, thierry.reding, treding, robh+dt,
catalin.marinas, krzysztof.kozlowski+dt, kuba, jonathanh, will
On Thu, 23 Jun 2022 13:16:10 +0530, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Tegra234 has multiple network interfaces with each their own memory
> clients and stream IDs to allow for proper isolation.
>
>
Applied, thanks!
[4/9] memory: tegra: Add MGBE memory clients for Tegra234
https://git.kernel.org/krzk/linux-mem-ctrl/c/6b36629c85dc7d4551e57e92a3e970d099333e4e
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: (subset) [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
@ 2022-06-24 16:24 ` Thierry Reding
2022-06-25 20:17 ` Krzysztof Kozlowski
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2022-06-24 16:24 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-tegra, netdev, devicetree, vbhadram, treding, robh+dt,
catalin.marinas, krzysztof.kozlowski+dt, kuba, jonathanh, will
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On Fri, Jun 24, 2022 at 06:06:35PM +0200, Krzysztof Kozlowski wrote:
> On Thu, 23 Jun 2022 13:16:10 +0530, Bhadram Varka wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Tegra234 has multiple network interfaces with each their own memory
> > clients and stream IDs to allow for proper isolation.
> >
> >
>
> Applied, thanks!
>
> [4/9] memory: tegra: Add MGBE memory clients for Tegra234
> https://git.kernel.org/krzk/linux-mem-ctrl/c/6b36629c85dc7d4551e57e92a3e970d099333e4e
Ah yes, you'll need the dt-bindings header for this driver bit as well.
If you don't mind I could pick all of these up into the Tegra tree and
resolve the dependencies there, then send a pull request for the memory
tree that incorporates the dt-bindings branch as a dependency.
That way you don't have to worry about this at all. We might also get
another set of similar changes for PCI or USB during this cycle, so it'd
certainly be easier to collect all of these in a central place.
Thierry
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: (subset) [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-06-24 16:24 ` Thierry Reding
@ 2022-06-25 20:17 ` Krzysztof Kozlowski
0 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-25 20:17 UTC (permalink / raw)
To: Thierry Reding
Cc: linux-tegra, netdev, devicetree, vbhadram, treding, robh+dt,
catalin.marinas, krzysztof.kozlowski+dt, kuba, jonathanh, will
On 24/06/2022 18:24, Thierry Reding wrote:
> On Fri, Jun 24, 2022 at 06:06:35PM +0200, Krzysztof Kozlowski wrote:
>> On Thu, 23 Jun 2022 13:16:10 +0530, Bhadram Varka wrote:
>>> From: Thierry Reding <treding@nvidia.com>
>>>
>>> Tegra234 has multiple network interfaces with each their own memory
>>> clients and stream IDs to allow for proper isolation.
>>>
>>>
>>
>> Applied, thanks!
>>
>> [4/9] memory: tegra: Add MGBE memory clients for Tegra234
>> https://git.kernel.org/krzk/linux-mem-ctrl/c/6b36629c85dc7d4551e57e92a3e970d099333e4e
>
> Ah yes, you'll need the dt-bindings header for this driver bit as well.
> If you don't mind I could pick all of these up into the Tegra tree and
> resolve the dependencies there, then send a pull request for the memory
> tree that incorporates the dt-bindings branch as a dependency.
>
> That way you don't have to worry about this at all. We might also get
> another set of similar changes for PCI or USB during this cycle, so it'd
> certainly be easier to collect all of these in a central place.
I cannot take DTS patches to the driver tree, so it's easier if you take
it and handle the dependencies.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234
2022-06-23 7:46 ` [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Bhadram Varka
2022-06-24 16:06 ` (subset) " Krzysztof Kozlowski
@ 2022-06-25 20:18 ` Krzysztof Kozlowski
1 sibling, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-25 20:18 UTC (permalink / raw)
To: Bhadram Varka, netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding
On 23/06/2022 09:46, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Tegra234 has multiple network interfaces with each their own memory
> clients and stream IDs to allow for proper isolation.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> ---
> drivers/memory/tegra/tegra234.c | 80 +++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Dropped from my tree.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (2 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 4/9] memory: tegra: Add MGBE memory clients for Tegra234 Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-28 19:55 ` Rob Herring
2022-06-23 7:46 ` [PATCH net-next v1 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Bhadram Varka
` (4 subsequent siblings)
8 siblings, 1 reply; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Bhadram Varka
Add device-tree binding documentation for the Tegra234 MGBE ethernet
controller.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
.../bindings/net/nvidia,tegra234-mgbe.yaml | 163 ++++++++++++++++++
1 file changed, 163 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
new file mode 100644
index 000000000000..d6db43e60ab8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
@@ -0,0 +1,163 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra234 MGBE Device Tree Bindings
+
+maintainers:
+ - Thierry Reding <treding@nvidia.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+
+ compatible:
+ const: nvidia,tegra234-mgbe
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: hypervisor
+ - const: mac
+ - const: xpcs
+
+ interrupts:
+ minItems: 1
+
+ interrupt-names:
+ items:
+ - const: common
+
+ clocks:
+ minItems: 12
+ maxItems: 12
+
+ clock-names:
+ minItems: 12
+ maxItems: 12
+ contains:
+ enum:
+ - mgbe
+ - mac
+ - mac-divider
+ - ptp-ref
+ - rx-input-m
+ - rx-input
+ - tx
+ - eee-pcs
+ - rx-pcs-input
+ - rx-pcs-m
+ - rx-pcs
+ - tx-pcs
+
+ resets:
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ contains:
+ enum:
+ - mac
+ - pcs
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ iommus:
+ maxItems: 1
+
+ power-domains:
+ items:
+ - description: MGBE power-domain
+
+ phy-handle: true
+
+ phy-mode: true
+
+ mdio:
+ $ref: mdio.yaml#
+ unevaluatedProperties: false
+ description:
+ Creates and registers an MDIO bus.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - phy-handle
+ - phy-mode
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra234-mc.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ ethernet@6800000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+
+ phy-handle = <&mgbe0_phy>;
+ phy-mode = "usxgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mgbe0_phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+
+ #phy-cells = <0>;
+ };
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-06-23 7:46 ` [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE Bhadram Varka
@ 2022-06-28 19:55 ` Rob Herring
2022-06-30 14:54 ` Thierry Reding
0 siblings, 1 reply; 25+ messages in thread
From: Rob Herring @ 2022-06-28 19:55 UTC (permalink / raw)
To: Bhadram Varka
Cc: netdev, devicetree, linux-tegra, krzysztof.kozlowski+dt,
thierry.reding, jonathanh, kuba, catalin.marinas, will
On Thu, Jun 23, 2022 at 01:16:11PM +0530, Bhadram Varka wrote:
> Add device-tree binding documentation for the Tegra234 MGBE ethernet
> controller.
>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> ---
> .../bindings/net/nvidia,tegra234-mgbe.yaml | 163 ++++++++++++++++++
> 1 file changed, 163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> new file mode 100644
> index 000000000000..d6db43e60ab8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> @@ -0,0 +1,163 @@
> +# SPDX-License-Identifier: GPL-2.0
Dual license. checkpatch.pl will tell you this.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra234 MGBE Device Tree Bindings
s/Device Tree Bindings/???bit Ethernet Controller/
> +
> +maintainers:
> + - Thierry Reding <treding@nvidia.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> +
> + compatible:
> + const: nvidia,tegra234-mgbe
> +
> + reg:
> + minItems: 3
> + maxItems: 3
> +
> + reg-names:
> + items:
> + - const: hypervisor
> + - const: mac
> + - const: xpcs
Is this really part of the same block? You don't have a PHY (the one in
front of the ethernet PHY) and PCS is sometimes part of the PHY.
> +
> + interrupts:
> + minItems: 1
> +
> + interrupt-names:
> + items:
> + - const: common
Just drop interrupt-names. Not a useful name really.
> +
> + clocks:
> + minItems: 12
> + maxItems: 12
> +
> + clock-names:
> + minItems: 12
> + maxItems: 12
> + contains:
> + enum:
> + - mgbe
> + - mac
> + - mac-divider
> + - ptp-ref
> + - rx-input-m
> + - rx-input
> + - tx
> + - eee-pcs
> + - rx-pcs-input
> + - rx-pcs-m
> + - rx-pcs
> + - tx-pcs
> +
> + resets:
> + minItems: 2
> + maxItems: 2
> +
> + reset-names:
> + contains:
> + enum:
> + - mac
> + - pcs
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + iommus:
> + maxItems: 1
> +
> + power-domains:
> + items:
> + - description: MGBE power-domain
What else would it be? Just 'maxItems: 1'.
> +
> + phy-handle: true
> +
> + phy-mode: true
All possible modes are supported by this h/w? Not likely.
> +
> + mdio:
> + $ref: mdio.yaml#
> + unevaluatedProperties: false
> + description:
> + Creates and registers an MDIO bus.
That's OS behavior...
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - phy-handle
> + - phy-mode
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra234-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/tegra234-mc.h>
> + #include <dt-bindings/power/tegra234-powergate.h>
> + #include <dt-bindings/reset/tegra234-reset.h>
> +
> + ethernet@6800000 {
> + compatible = "nvidia,tegra234-mgbe";
> + reg = <0x06800000 0x10000>,
> + <0x06810000 0x10000>,
> + <0x068a0000 0x10000>;
> + reg-names = "hypervisor", "mac", "xpcs";
> + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common";
> + clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
> + <&bpmp TEGRA234_CLK_MGBE0_MAC>,
> + <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
> + <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
> + <&bpmp TEGRA234_CLK_MGBE0_TX>,
> + <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
> + <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
> + <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
> + clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
> + "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
> + "rx-pcs", "tx-pcs";
> + resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
> + <&bpmp TEGRA234_RESET_MGBE0_PCS>;
> + reset-names = "mac", "pcs";
> + interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
> + <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
> + interconnect-names = "dma-mem", "write";
> + iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
> + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
> +
> + phy-handle = <&mgbe0_phy>;
> + phy-mode = "usxgmii";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mgbe0_phy: phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c45";
> + reg = <0x0>;
> +
> + #phy-cells = <0>;
> + };
> + };
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-06-28 19:55 ` Rob Herring
@ 2022-06-30 14:54 ` Thierry Reding
2022-07-07 4:10 ` Bhadram Varka
0 siblings, 1 reply; 25+ messages in thread
From: Thierry Reding @ 2022-06-30 14:54 UTC (permalink / raw)
To: Rob Herring, Bhadram Varka
Cc: netdev, devicetree, linux-tegra, krzysztof.kozlowski+dt,
jonathanh, kuba, catalin.marinas, will
[-- Attachment #1: Type: text/plain, Size: 5254 bytes --]
On Tue, Jun 28, 2022 at 01:55:34PM -0600, Rob Herring wrote:
> On Thu, Jun 23, 2022 at 01:16:11PM +0530, Bhadram Varka wrote:
> > Add device-tree binding documentation for the Tegra234 MGBE ethernet
> > controller.
> >
> > Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> > ---
> > .../bindings/net/nvidia,tegra234-mgbe.yaml | 163 ++++++++++++++++++
> > 1 file changed, 163 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> > new file mode 100644
> > index 000000000000..d6db43e60ab8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> > @@ -0,0 +1,163 @@
> > +# SPDX-License-Identifier: GPL-2.0
>
> Dual license. checkpatch.pl will tell you this.
>
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Tegra234 MGBE Device Tree Bindings
>
> s/Device Tree Bindings/???bit Ethernet Controller/
>
> > +
> > +maintainers:
> > + - Thierry Reding <treding@nvidia.com>
> > + - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +properties:
> > +
> > + compatible:
> > + const: nvidia,tegra234-mgbe
> > +
> > + reg:
> > + minItems: 3
> > + maxItems: 3
> > +
> > + reg-names:
> > + items:
> > + - const: hypervisor
> > + - const: mac
> > + - const: xpcs
>
> Is this really part of the same block? You don't have a PHY (the one in
> front of the ethernet PHY) and PCS is sometimes part of the PHY.
Yes, these are all part of the same block. As an example, the MGBE0
instantiation of this block on Tegra234 is assigned an address space
from 0x06800000 to 0x068fffff. Within that there are three main sections
of registers:
MAC 0x06800000-0x0689ffff
PCS 0x068a0000-0x068bffff
SEC 0x068c0000-0x068effff
Each of these are further subdivided (hypervisor and mac are within that
MAC section, while XPCS is in the PCS section) and we don't have reg
entries for all of them because things like SEC and virtualization
aren't supported upstream yet.
> > +
> > + interrupts:
> > + minItems: 1
> > +
> > + interrupt-names:
> > + items:
> > + - const: common
>
> Just drop interrupt-names. Not a useful name really.
There will eventually be other interrupts that could be used here. For
example there are five additional interrupts that are used for
virtualization and another two for the MACSEC module. Neither of which
are supported in upstream at the moment, so we didn't want to define
these yet. However, specifying the interrupt-names property from the
start, it will allow these other interrupts to be added in a backwards-
compatible and easy way later on.
>
> > +
> > + clocks:
> > + minItems: 12
> > + maxItems: 12
> > +
> > + clock-names:
> > + minItems: 12
> > + maxItems: 12
> > + contains:
> > + enum:
> > + - mgbe
> > + - mac
> > + - mac-divider
> > + - ptp-ref
> > + - rx-input-m
> > + - rx-input
> > + - tx
> > + - eee-pcs
> > + - rx-pcs-input
> > + - rx-pcs-m
> > + - rx-pcs
> > + - tx-pcs
> > +
> > + resets:
> > + minItems: 2
> > + maxItems: 2
> > +
> > + reset-names:
> > + contains:
> > + enum:
> > + - mac
> > + - pcs
> > +
> > + interconnects:
> > + items:
> > + - description: memory read client
> > + - description: memory write client
> > +
> > + interconnect-names:
> > + items:
> > + - const: dma-mem # read
> > + - const: write
> > +
> > + iommus:
> > + maxItems: 1
> > +
> > + power-domains:
> > + items:
> > + - description: MGBE power-domain
>
> What else would it be? Just 'maxItems: 1'.
It's possible that we have some generic descriptions like this in other
bindings, but I agree that this doesn't add anything useful. I can look
into other bindings and remove these generic descriptions so that they
don't set a bad example.
> > +
> > + phy-handle: true
> > +
> > + phy-mode: true
>
> All possible modes are supported by this h/w? Not likely.
>
> > +
> > + mdio:
> > + $ref: mdio.yaml#
> > + unevaluatedProperties: false
> > + description:
> > + Creates and registers an MDIO bus.
>
> That's OS behavior...
I suppose we can just leave out the description here because this is
fairly standard.
Bhadram, can you address the comments in this and send out a v2 of the
whole series? As suggested by Jakub, let's either leave out the driver
bits at this point so as not to confuse maintainers any further, or at
least make sure that the driver patch is the last one in the series to
make it a bit more obvious what needs to be applied to net/next.
Also, keep in mind that if we want to get this into v5.20, we need to
get the bindings finalized in the next couple of days.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* RE: [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE
2022-06-30 14:54 ` Thierry Reding
@ 2022-07-07 4:10 ` Bhadram Varka
0 siblings, 0 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-07-07 4:10 UTC (permalink / raw)
To: Thierry Reding, Rob Herring
Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org,
Jonathan Hunter, kuba@kernel.org, catalin.marinas@arm.com,
will@kernel.org
Hi @Rob Herring,
Thanks for the review.
> -----Original Message-----
> From: Thierry Reding <thierry.reding@gmail.com>
> Sent: 30 June 2022 08:25 PM
> To: Rob Herring <robh@kernel.org>; Bhadram Varka
> <vbhadram@nvidia.com>
> Cc: netdev@vger.kernel.org; devicetree@vger.kernel.org; linux-
> tegra@vger.kernel.org; krzysztof.kozlowski+dt@linaro.org; Jonathan Hunter
> <jonathanh@nvidia.com>; kuba@kernel.org; catalin.marinas@arm.com;
> will@kernel.org
> Subject: Re: [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE
>
> On Tue, Jun 28, 2022 at 01:55:34PM -0600, Rob Herring wrote:
> > On Thu, Jun 23, 2022 at 01:16:11PM +0530, Bhadram Varka wrote:
> > > Add device-tree binding documentation for the Tegra234 MGBE ethernet
> > > controller.
> > >
> > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> > > Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
> > > ---
> > > .../bindings/net/nvidia,tegra234-mgbe.yaml | 163
> ++++++++++++++++++
> > > 1 file changed, 163 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> > > b/Documentation/devicetree/bindings/net/nvidia,tegra234-mgbe.yaml
> > > new file mode 100644
> > > index 000000000000..d6db43e60ab8
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/net/nvidia,tegra234-
> mgbe.yam
> > > +++ l
> > > @@ -0,0 +1,163 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> >
> > Dual license. checkpatch.pl will tell you this.
Addressed this comment.
> >
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Tegra234 MGBE Device Tree Bindings
> >
> > s/Device Tree Bindings/???bit Ethernet Controller/
Addressed this comment
> >
> > > +
> > > +maintainers:
> > > + - Thierry Reding <treding@nvidia.com>
> > > + - Jon Hunter <jonathanh@nvidia.com>
> > > +
> > > +properties:
> > > +
> > > + compatible:
> > > + const: nvidia,tegra234-mgbe
> > > +
> > > + reg:
> > > + minItems: 3
> > > + maxItems: 3
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: hypervisor
> > > + - const: mac
> > > + - const: xpcs
> >
> > Is this really part of the same block? You don't have a PHY (the one
> > in front of the ethernet PHY) and PCS is sometimes part of the PHY.
>
> Yes, these are all part of the same block. As an example, the MGBE0
> instantiation of this block on Tegra234 is assigned an address space from
> 0x06800000 to 0x068fffff. Within that there are three main sections of
> registers:
>
> MAC 0x06800000-0x0689ffff
> PCS 0x068a0000-0x068bffff
> SEC 0x068c0000-0x068effff
>
> Each of these are further subdivided (hypervisor and mac are within that
> MAC section, while XPCS is in the PCS section) and we don't have reg entries
> for all of them because things like SEC and virtualization aren't supported
> upstream yet.
>
> > > +
> > > + interrupts:
> > > + minItems: 1
> > > +
> > > + interrupt-names:
> > > + items:
> > > + - const: common
> >
> > Just drop interrupt-names. Not a useful name really.
>
> There will eventually be other interrupts that could be used here. For
> example there are five additional interrupts that are used for virtualization
> and another two for the MACSEC module. Neither of which are supported in
> upstream at the moment, so we didn't want to define these yet. However,
> specifying the interrupt-names property from the start, it will allow these
> other interrupts to be added in a backwards- compatible and easy way later
> on.
>
> >
> > > +
> > > + clocks:
> > > + minItems: 12
> > > + maxItems: 12
> > > +
> > > + clock-names:
> > > + minItems: 12
> > > + maxItems: 12
> > > + contains:
> > > + enum:
> > > + - mgbe
> > > + - mac
> > > + - mac-divider
> > > + - ptp-ref
> > > + - rx-input-m
> > > + - rx-input
> > > + - tx
> > > + - eee-pcs
> > > + - rx-pcs-input
> > > + - rx-pcs-m
> > > + - rx-pcs
> > > + - tx-pcs
> > > +
> > > + resets:
> > > + minItems: 2
> > > + maxItems: 2
> > > +
> > > + reset-names:
> > > + contains:
> > > + enum:
> > > + - mac
> > > + - pcs
> > > +
> > > + interconnects:
> > > + items:
> > > + - description: memory read client
> > > + - description: memory write client
> > > +
> > > + interconnect-names:
> > > + items:
> > > + - const: dma-mem # read
> > > + - const: write
> > > +
> > > + iommus:
> > > + maxItems: 1
> > > +
> > > + power-domains:
> > > + items:
> > > + - description: MGBE power-domain
> >
> > What else would it be? Just 'maxItems: 1'.
>
> It's possible that we have some generic descriptions like this in other
> bindings, but I agree that this doesn't add anything useful. I can look into
> other bindings and remove these generic descriptions so that they don't set
> a bad example.
>
> > > +
> > > + phy-handle: true
> > > +
> > > + phy-mode: true
> >
> > All possible modes are supported by this h/w? Not likely.
Updated the comments to reflect usxgmii and xfi
> >
> > > +
> > > + mdio:
> > > + $ref: mdio.yaml#
> > > + unevaluatedProperties: false
> > > + description:
> > > + Creates and registers an MDIO bus.
> >
> > That's OS behavior...
>
> I suppose we can just leave out the description here because this is fairly
> standard.
>
> Bhadram, can you address the comments in this and send out a v2 of the
> whole series? As suggested by Jakub, let's either leave out the driver bits at
> this point so as not to confuse maintainers any further, or at least make sure
> that the driver patch is the last one in the series to make it a bit more obvious
> what needs to be applied to net/next.
>
Okay.
> Also, keep in mind that if we want to get this into v5.20, we need to get the
> bindings finalized in the next couple of days.
>
> Thierry
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH net-next v1 6/9] arm64: tegra: Add MGBE nodes on Tegra234
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (3 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 5/9] dt-bindings: net: Add Tegra234 MGBE Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Bhadram Varka
` (3 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding, Bhadram Varka
From: Thierry Reding <treding@nvidia.com>
Add MGBE IP DT nodes in SOC DT files.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 136 +++++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index cb3af539e477..b77b55e80223 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -791,6 +791,142 @@
#mbox-cells = <2>;
};
+ ethernet@6800000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06800000 0x10000>,
+ <0x06810000 0x10000>,
+ <0x068a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX>,
+ <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE0_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
+ status = "disabled";
+ };
+
+ ethernet@6900000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06900000 0x10000>,
+ <0x06910000 0x10000>,
+ <0x069a0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX>,
+ <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE1_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
+ status = "disabled";
+ };
+
+ ethernet@6a00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06a00000 0x10000>,
+ <0x06a10000 0x10000>,
+ <0x06aa0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX>,
+ <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE2_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
+ status = "disabled";
+ };
+
+ ethernet@6b00000 {
+ compatible = "nvidia,tegra234-mgbe";
+ reg = <0x06b00000 0x10000>,
+ <0x06b10000 0x10000>,
+ <0x06ba0000 0x10000>;
+ reg-names = "hypervisor", "mac", "xpcs";
+ interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common";
+ clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC>,
+ <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
+ <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX>,
+ <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
+ <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
+ <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
+ clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
+ "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
+ "rx-pcs", "tx-pcs";
+ resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
+ <&bpmp TEGRA234_RESET_MGBE3_PCS>;
+ reset-names = "mac", "pcs";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
+ status = "disabled";
+ };
+
smmu_niso1: iommu@8000000 {
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
reg = <0x8000000 0x1000000>,
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH net-next v1 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (4 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 6/9] arm64: tegra: Add MGBE nodes on Tegra234 Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-23 7:46 ` [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support Bhadram Varka
` (2 subsequent siblings)
8 siblings, 0 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding, Bhadram Varka
From: Thierry Reding <treding@nvidia.com>
Change enables MGBE on Jetson AGX Orin Developer Kit
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index eaf1994abb04..8e2618a902ab 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -1976,6 +1976,27 @@
stdout-path = "serial0:115200n8";
};
+ bus@0 {
+ ethernet@6800000 {
+ status = "okay";
+
+ phy-handle = <&mgbe0_phy>;
+ phy-mode = "usxgmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mgbe0_phy: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x0>;
+
+ #phy-cells = <0>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
status = "okay";
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (5 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 7/9] arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-24 18:16 ` Jakub Kicinski
2022-06-23 7:46 ` [PATCH net-next v1 9/9] arm64: defconfig: Enable Tegra MGBE driver Bhadram Varka
2022-06-24 16:02 ` [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Krzysztof Kozlowski
8 siblings, 1 reply; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Bhadram Varka, Thierry Reding
Add MGBE/XPCS IP support which founds on Tegra234 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 +
drivers/net/ethernet/stmicro/stmmac/Makefile | 1 +
.../net/ethernet/stmicro/stmmac/dwmac-tegra.c | 294 ++++++++++++++++++
3 files changed, 301 insertions(+)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 31ff35174034..e9f61bdaf7c4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -235,6 +235,12 @@ config DWMAC_INTEL_PLAT
the stmmac device driver. This driver is used for the Intel Keem Bay
SoC.
+config DWMAC_TEGRA
+ tristate "NVIDIA Tegra MGBE support"
+ depends on ARCH_TEGRA || COMPILE_TEST
+ help
+ Support for the MGBE controller found on Tegra SoCs.
+
config DWMAC_VISCONTI
tristate "Toshiba Visconti DWMAC support"
default ARCH_VISCONTI
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index d4e12e9ace4f..057e4bab5c08 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o
obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o
obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o
+obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o
obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o
stmmac-platform-objs:= stmmac_platform.o
dwmac-altr-socfpga-objs := altr_tse_pcs.o dwmac-socfpga.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
new file mode 100644
index 000000000000..641b8773428a
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/platform_device.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/stmmac.h>
+#include <linux/clk.h>
+
+#include "stmmac_platform.h"
+
+static const char *const mgbe_clks[] = {
+ "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
+};
+
+struct tegra_mgbe {
+ struct device *dev;
+
+ struct clk_bulk_data *clks;
+
+ struct reset_control *rst_mac;
+ struct reset_control *rst_pcs;
+
+ void __iomem *hv;
+ void __iomem *regs;
+ void __iomem *xpcs;
+
+ struct mii_bus *mii;
+};
+
+
+#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
+#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
+#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
+#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
+#define XPCS_WRAP_UPHY_STATUS 0x8044
+#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
+#define XPCS_WRAP_IRQ_STATUS 0x8050
+#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)
+
+#define XPCS_REG_ADDR_SHIFT 10
+#define XPCS_REG_ADDR_MASK 0x1fff
+#define XPCS_ADDR 0x3fc
+
+#define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704
+#define MAC_SBD_INTR BIT(2)
+#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
+#define MGBE_SID 0x6
+
+static void mgbe_uphy_lane_bringup(struct tegra_mgbe *mgbe)
+{
+ unsigned int retry = 300;
+ u32 value;
+ int err;
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
+ if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
+ value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
+ }
+
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
+ (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
+ 500, 500 * 2000);
+ if (err < 0) {
+ dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
+ }
+
+ usleep_range(10000, 20000);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
+ (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
+ 1000, 1000 * 2000);
+ if (err < 0) {
+ dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
+ }
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+ value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
+ writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
+
+ while (--retry) {
+ err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
+ value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
+ 500, 500 * 2000);
+ if (err < 0) {
+ dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
+ usleep_range(10000, 20000);
+ continue;
+ }
+ break;
+ }
+
+ /* clear status */
+ writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);
+}
+
+static int tegra_mgbe_probe(struct platform_device *pdev)
+{
+ struct plat_stmmacenet_data *plat;
+ struct stmmac_resources res;
+ struct tegra_mgbe *mgbe;
+ int irq, err, i;
+
+ mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
+ if (!mgbe)
+ return -ENOMEM;
+
+ mgbe->dev = &pdev->dev;
+
+ memset(&res, 0, sizeof(res));
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
+ if (IS_ERR(mgbe->hv))
+ return PTR_ERR(mgbe->hv);
+
+ mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
+ if (IS_ERR(mgbe->regs))
+ return PTR_ERR(mgbe->regs);
+
+ mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
+ if (IS_ERR(mgbe->xpcs))
+ return PTR_ERR(mgbe->xpcs);
+
+ res.addr = mgbe->regs;
+ res.irq = irq;
+
+ mgbe->clks = devm_kzalloc(&pdev->dev, sizeof(*mgbe->clks), GFP_KERNEL);
+ if (!mgbe->clks)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(mgbe_clks); i++)
+ mgbe->clks[i].id = mgbe_clks[i];
+
+ err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
+ if (err < 0)
+ return err;
+
+ err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
+ if (err < 0)
+ return err;
+
+ /* Perform MAC reset */
+ mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
+ if (IS_ERR(mgbe->rst_mac))
+ return PTR_ERR(mgbe->rst_mac);
+
+ err = reset_control_assert(mgbe->rst_mac);
+ if (err < 0)
+ return err;
+
+ usleep_range(2000, 4000);
+
+ err = reset_control_deassert(mgbe->rst_mac);
+ if (err < 0)
+ return err;
+
+ /* Perform PCS reset */
+ mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
+ if (IS_ERR(mgbe->rst_pcs))
+ return PTR_ERR(mgbe->rst_pcs);
+
+ err = reset_control_assert(mgbe->rst_pcs);
+ if (err < 0)
+ return err;
+
+ usleep_range(2000, 4000);
+
+ err = reset_control_deassert(mgbe->rst_pcs);
+ if (err < 0)
+ return err;
+
+ plat = stmmac_probe_config_dt(pdev, res.mac);
+ if (IS_ERR(plat))
+ return PTR_ERR(plat);
+
+ plat->has_xgmac = 1;
+ plat->tso_en = 1;
+ plat->pmt = 1;
+ plat->bsp_priv = mgbe;
+
+ if (!plat->mdio_node) {
+ plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");
+ }
+
+ if (!plat->mdio_bus_data) {
+ plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
+ GFP_KERNEL);
+ if (!plat->mdio_bus_data) {
+ err = -ENOMEM;
+ goto remove;
+ }
+ }
+
+ plat->mdio_bus_data->needs_reset = true;
+
+ mgbe_uphy_lane_bringup(mgbe);
+
+ /* Tx FIFO Size - 128KB */
+ plat->tx_fifo_size = 131072;
+ /* Rx FIFO Size - 192KB */
+ plat->rx_fifo_size = 196608;
+
+ /* Enable common interrupt at wrapper level */
+ writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);
+
+ /* Program SID */
+ writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);
+
+ err = stmmac_dvr_probe(&pdev->dev, plat, &res);
+ if (err < 0)
+ goto remove;
+
+ return 0;
+
+remove:
+ stmmac_remove_config_dt(pdev, plat);
+ return err;
+}
+
+static int tegra_mgbe_remove(struct platform_device *pdev)
+{
+ struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);
+
+ clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
+
+ stmmac_pltfr_remove(pdev);
+
+ return 0;
+}
+
+static const struct of_device_id tegra_mgbe_match[] = {
+ { .compatible = "nvidia,tegra234-mgbe", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, tegra_mgbe_match);
+
+static struct platform_driver tegra_mgbe_driver = {
+ .probe = tegra_mgbe_probe,
+ .remove = tegra_mgbe_remove,
+ .driver = {
+ .name = "tegra-mgbe",
+ .pm = &stmmac_pltfr_pm_ops,
+ .of_match_table = tegra_mgbe_match,
+ },
+};
+module_platform_driver(tegra_mgbe_driver);
+
+MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support
2022-06-23 7:46 ` [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support Bhadram Varka
@ 2022-06-24 18:16 ` Jakub Kicinski
0 siblings, 0 replies; 25+ messages in thread
From: Jakub Kicinski @ 2022-06-24 18:16 UTC (permalink / raw)
To: Bhadram Varka
Cc: netdev, devicetree, linux-tegra, robh+dt, krzysztof.kozlowski+dt,
thierry.reding, jonathanh, catalin.marinas, will, Thierry Reding
On Thu, 23 Jun 2022 13:16:14 +0530 Bhadram Varka wrote:
> Add MGBE/XPCS IP support which founds on Tegra234 SoCs.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Please repost the actual net-next material once the dust settles
on folks picking stuff out to their trees.
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH net-next v1 9/9] arm64: defconfig: Enable Tegra MGBE driver
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (6 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 8/9] stmmac: tegra: Add MGBE support Bhadram Varka
@ 2022-06-23 7:46 ` Bhadram Varka
2022-06-24 16:02 ` [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Krzysztof Kozlowski
8 siblings, 0 replies; 25+ messages in thread
From: Bhadram Varka @ 2022-06-23 7:46 UTC (permalink / raw)
To: netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Bhadram Varka
Enable Tegra MGBE driver which found on T234 SoC's.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7d1105343bc2..f80142abd9c6 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -359,6 +359,7 @@ CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
+CONFIG_DWMAC_TEGRA=m
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
--
2.17.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains
2022-06-23 7:46 [PATCH net-next v1 1/9] dt-bindings: power: Add Tegra234 MGBE power domains Bhadram Varka
` (7 preceding siblings ...)
2022-06-23 7:46 ` [PATCH net-next v1 9/9] arm64: defconfig: Enable Tegra MGBE driver Bhadram Varka
@ 2022-06-24 16:02 ` Krzysztof Kozlowski
8 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24 16:02 UTC (permalink / raw)
To: Bhadram Varka, netdev, devicetree, linux-tegra
Cc: robh+dt, krzysztof.kozlowski+dt, thierry.reding, jonathanh, kuba,
catalin.marinas, will, Thierry Reding
On 23/06/2022 09:46, Bhadram Varka wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Add power domain IDs for the four MGBE power partitions found on
> Tegra234.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread