[Intel-gfx] [PATCH v3 0/9] DG2 VRAM_SR Support

[Intel-gfx] [PATCH v3 0/9] DG2 VRAM_SR Support

[Anshuman Gupta]

This series add DG2 D3Cold VRAM_SR support.

TODO: GT and GuC Interface state save/restore on VRAM_SR entry/exit.

Anshuman Gupta (8):
  drm/i915/dgfx: OpRegion VRAM Self Refresh Support
  drm/i915/dg1: OpRegion PCON DG1 MBD config support
  drm/i915/dg2: Add DG2_NB_MBD subplatform
  drm/i915/dg2: DG2 MBD config
  drm/i915/dgfx: Add has_lmem_sr
  drm/i915/dgfx: Setup VRAM SR with D3COLD
  Drm/i915/rpm: Enable D3Cold VRAM SR Support
  drm/i915/rpm: d3cold Policy

Tvrtko Ursulin (1):
  drm/i915/xehpsdv: Store lmem region in gt

 drivers/gpu/drm/i915/display/intel_opregion.c | 101 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h |  17 +++
 drivers/gpu/drm/i915/gt/intel_gt.c            |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   3 +
 drivers/gpu/drm/i915/i915_driver.c            |  25 +++++
 drivers/gpu/drm/i915/i915_drv.h               |   5 +
 drivers/gpu/drm/i915/i915_params.c            |   4 +
 drivers/gpu/drm/i915/i915_params.h            |   1 +
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_device_info.c      |  14 +++
 drivers/gpu/drm/i915/intel_device_info.h      |   4 +-
 drivers/gpu/drm/i915/intel_pcode.h            |   1 +
 drivers/gpu/drm/i915/intel_pm.c               |  95 ++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h               |   3 +
 drivers/gpu/drm/i915/intel_runtime_pm.c       |   3 +-
 drivers/gpu/drm/i915/intel_runtime_pm.h       |   7 ++
 include/drm/i915_pciids.h                     |  23 ++--
 18 files changed, 302 insertions(+), 11 deletions(-)

-- 
2.26.2

[Intel-gfx] [PATCH v3 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Anshuman Gupta]

Intel DGFX cards provides a feature Video Ram Self Refrsh(vram_sr).
vram_sr can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.

vram_sr feature requires Host BIOS support, vram_sr will be
enable/disable by HOST BIOS using ACPI OpRegion.

OpRegion vram_sr is only applicable on Motherboard Down
cards.

Adding OpRegion vram_sr support in order to enable/disable
vram_sr on discrete cards.

v2:
- Added opregion->header NULL check. [Jani]
- Bundled opregion->asle NULL check to early return. [Jani]
- Use static inline for dummy declaration. [Jani]

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 78 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h | 17 ++++
 2 files changed, 94 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 1c0c745c142d..f4a2a02c9ed3 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -55,6 +55,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
 
 struct opregion_header {
@@ -132,7 +134,8 @@ struct opregion_asle {
 	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
 			 * address of raw VBT data. */
 	u32 rvds;	/* Size of raw vbt data */
-	u8 rsvd[58];
+	u8 vrsr;	/* DGFX Video Ram Self Refresh */
+	u8 rsvd[57];
 } __packed;
 
 /* OpRegion mailbox #5: ASLE ext */
@@ -203,6 +206,9 @@ struct opregion_asle_ext {
 
 #define ASLE_PHED_EDID_VALID_MASK	0x3
 
+/* VRAM SR */
+#define ASLE_VRSR_ENABLE		BIT(0)
+
 /* Software System Control Interrupt (SWSCI) */
 #define SWSCI_SCIC_INDICATOR		(1 << 0)
 #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
@@ -923,6 +929,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 		opregion->header->over.minor,
 		opregion->header->over.revision);
 
+	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon);
+
 	mboxes = opregion->header->mboxes;
 	if (mboxes & MBOX_ACPI) {
 		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
@@ -1248,3 +1256,71 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->vbt = NULL;
 	opregion->lid_state = NULL;
 }
+
+/**
+ * intel_opregion_vram_sr_required().
+ * @i915 i915 device priv data.
+ *
+ * It checks whether a DGFX card is Mother Board Down config depending
+ * on respective discrete platform.
+ *
+ * Returns:
+ * It returns a boolean whether opregion vram_sr support is required.
+ */
+bool
+intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	return false;
+}
+
+/**
+ * intel_opregion_bios_supports_vram_sr() - get HOST BIOS vram_sr
+ * capability support.
+ * @i915: pointer to i915 device.
+ *
+ * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
+ * capability support. It is only applocable to DGFX.
+ *
+ * Returns:
+ * true when bios supports vram_sr, or false if bios doesn't support.
+ */
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (!opregion->header)
+		return false;
+
+	if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
+		return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr() - enable/disable vram_sr.
+ * @i915: pointer to i915 device.
+ * @enable: Argument to enable/disable vram_sr.
+ *
+ * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
+ * HOST BIOS will enables and disbales VRAM_SR during
+ * ACPI _PS3/_OFF and _PS/_ON glue method.
+ */
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!opregion->header || !opregion->asle)
+		return;
+
+	if (!intel_opregion_vram_sr_required(i915))
+		return;
+
+	if (enable)
+		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
+	else
+		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 2f261f985400..55a61e8a28dc 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -75,6 +75,9 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
 				  pci_power_t state);
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
+bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -134,6 +137,20 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
 	return false;
 }
 
+static inline bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	return false;
+}
+
+static inline bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	return false;
+}
+
+static inline void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[Intel-gfx] [PATCH v3 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Anshuman Gupta]

DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable vram_sr using ACPI OpRegion.

i915 requires to check OpRegion PCON MBD Config bits to
discover whether DG1 Card is MBD config before enabling
vram_sr.

v2:
- Removed IS_DG1() cond from intel_opregion_dg1_mbd_config. [Jani]
- Moved intel_opregion_vram_sr_required() to prev patch.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index f4a2a02c9ed3..03ae57f05371 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -55,6 +55,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DG1_MBD_CONFIG				BIT(9)
+#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
@@ -1257,6 +1259,19 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->lid_state = NULL;
 }
 
+static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!opregion->header)
+		return false;
+
+	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
+		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
+	else
+		return false;
+}
+
 /**
  * intel_opregion_vram_sr_required().
  * @i915 i915 device priv data.
@@ -1270,6 +1285,12 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 bool
 intel_opregion_vram_sr_required(struct drm_i915_private *i915)
 {
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (IS_DG1(i915))
+		return intel_opregion_dg1_mbd_config(i915);
+
 	return false;
 }
 
-- 
2.26.2

[Intel-gfx] [PATCH v3 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Anshuman Gupta]

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

v2:
- Adding only required MBD subplatform. [Jani, Matt]

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/intel_device_info.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  3 ++-
 include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
 4 files changed, 34 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c22f29c3faa0..a68777948db9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1012,6 +1012,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+#define IS_DG2_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_MBD)
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..4490977a3322 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -189,16 +189,25 @@ static const u16 subplatform_rpl_ids[] = {
 
 static const u16 subplatform_g10_ids[] = {
 	INTEL_DG2_G10_IDS(0),
+	INTEL_DG2_G10_NB_MBD_IDS(0),
 	INTEL_ATS_M150_IDS(0),
 };
 
 static const u16 subplatform_g11_ids[] = {
 	INTEL_DG2_G11_IDS(0),
+	INTEL_DG2_G11_NB_MBD_IDS(0),
 	INTEL_ATS_M75_IDS(0),
 };
 
 static const u16 subplatform_g12_ids[] = {
 	INTEL_DG2_G12_IDS(0),
+	INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_mbd_ids[] = {
+	INTEL_DG2_G10_NB_MBD_IDS(0),
+	INTEL_DG2_G11_NB_MBD_IDS(0),
+	INTEL_DG2_G12_NB_MBD_IDS(0),
 };
 
 static bool find_devid(u16 id, const u16 *p, unsigned int num)
@@ -257,6 +266,11 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 		mask = BIT(INTEL_SUBPLATFORM_G12);
 	}
 
+	if (find_devid(devid, subplatform_mbd_ids,
+		       ARRAY_SIZE(subplatform_mbd_ids))) {
+		mask |= BIT(INTEL_SUBPLATFORM_MBD);
+	}
+
 	GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
 
 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..6c9564429509 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
  * it is fine for the same bit to be used on multiple parent platforms.
  */
 
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (4)
 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 
 /* HSW/BDW/SKL/KBL/CFL */
@@ -114,6 +114,7 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_G10	0
 #define INTEL_SUBPLATFORM_G11	1
 #define INTEL_SUBPLATFORM_G12	2
+#define INTEL_SUBPLATFORM_MBD	3
 
 /* ADL */
 #define INTEL_SUBPLATFORM_RPL	0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..198be417bb2d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -693,32 +693,41 @@
 	INTEL_VGA_DEVICE(0xA7A9, info)
 
 /* DG2 */
-#define INTEL_DG2_G10_IDS(info) \
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
 	INTEL_VGA_DEVICE(0x5690, info), \
 	INTEL_VGA_DEVICE(0x5691, info), \
-	INTEL_VGA_DEVICE(0x5692, info), \
+	INTEL_VGA_DEVICE(0x5692, info)
+
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5693, info), \
+	INTEL_VGA_DEVICE(0x5694, info), \
+	INTEL_VGA_DEVICE(0x5695, info)
+
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5696, info), \
+	INTEL_VGA_DEVICE(0x5697, info)
+
+#define INTEL_DG2_G10_IDS(info) \
 	INTEL_VGA_DEVICE(0x56A0, info), \
 	INTEL_VGA_DEVICE(0x56A1, info), \
 	INTEL_VGA_DEVICE(0x56A2, info)
 
 #define INTEL_DG2_G11_IDS(info) \
-	INTEL_VGA_DEVICE(0x5693, info), \
-	INTEL_VGA_DEVICE(0x5694, info), \
-	INTEL_VGA_DEVICE(0x5695, info), \
 	INTEL_VGA_DEVICE(0x56A5, info), \
 	INTEL_VGA_DEVICE(0x56A6, info), \
 	INTEL_VGA_DEVICE(0x56B0, info), \
 	INTEL_VGA_DEVICE(0x56B1, info)
 
 #define INTEL_DG2_G12_IDS(info) \
-	INTEL_VGA_DEVICE(0x5696, info), \
-	INTEL_VGA_DEVICE(0x5697, info), \
 	INTEL_VGA_DEVICE(0x56A3, info), \
 	INTEL_VGA_DEVICE(0x56A4, info), \
 	INTEL_VGA_DEVICE(0x56B2, info), \
 	INTEL_VGA_DEVICE(0x56B3, info)
 
 #define INTEL_DG2_IDS(info) \
+	INTEL_DG2_G10_NB_MBD_IDS(info), \
+	INTEL_DG2_G11_NB_MBD_IDS(info), \
+	INTEL_DG2_G12_NB_MBD_IDS(info), \
 	INTEL_DG2_G10_IDS(info), \
 	INTEL_DG2_G11_IDS(info), \
 	INTEL_DG2_G12_IDS(info)
-- 
2.26.2

[Intel-gfx] [PATCH v3 4/9] drm/i915/dg2: DG2 MBD config

[Anshuman Gupta]

Add DG2 Motherboard Down Config check condition
to intel_opregion_vram_sr_required().

v2:
- Use MBD Subplatform to check DG2 MBD. [Jani]

BSpec: 44477
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 03ae57f05371..ae0862bf10a5 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1290,6 +1290,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915)
 
 	if (IS_DG1(i915))
 		return intel_opregion_dg1_mbd_config(i915);
+	else if (IS_DG2_MBD(i915))
+		return true;
 
 	return false;
 }
-- 
2.26.2

[Intel-gfx] [PATCH v3 5/9] drm/i915/dgfx: Add has_lmem_sr

[Anshuman Gupta]

Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
is stable.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 1 +
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a68777948db9..80de5b2eaf53 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1301,6 +1301,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..04aad54033dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = {
 	DGFX_FEATURES,
 	.graphics.rel = 10,
 	PLATFORM(INTEL_DG1),
+	.has_lmem_sr = 0,
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
 	.platform_engine_mask =
@@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
 	XE_LPD_FEATURES,
+	.has_lmem_sr = 1,
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	.require_force_probe = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6c9564429509..0b2dde67b8f8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -155,6 +155,7 @@ enum intel_ppgtt_type {
 	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
+	func(has_lmem_sr); \
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
-- 
2.26.2

[Intel-gfx] [PATCH v3 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Anshuman Gupta]

Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit.

v2:
- Moved intel_pcode_enable_vram_sr to intel_pm.c. [Jani]
- Removed vram_sr.lock. [Jani]
- Dropped Redundant !HAS_LMEM_SR(i915). [Jani]

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h    |  2 ++
 drivers/gpu/drm/i915/i915_reg.h    |  4 +++
 drivers/gpu/drm/i915/intel_pcode.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c    | 45 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h    |  2 ++
 6 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index be932a6d9c7d..1bc6227c0287 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -652,6 +652,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto err_msi;
 
+	intel_pm_vram_sr_setup(dev_priv);
+
 	/*
 	 * Fill the dram structure to get the system dram info. This will be
 	 * used for memory latency calculation.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 80de5b2eaf53..4f6694890c85 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,8 @@ struct drm_i915_private {
 	u32 bxt_phy_grc;
 
 	u32 suspend_count;
+	bool vram_sr_supported;
+
 	struct i915_suspend_saved_registers regfile;
 	struct vlv_s0ix_state *vlv_s0ix_state;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..0e3dc4a8846a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6766,6 +6766,8 @@
 #define   DG1_PCODE_STATUS			0x7E
 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   DG1_PCODE_D3_VRAM_SR                  0x71
+#define     DG1_ENABLE_SR                        0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
 /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
@@ -6779,6 +6781,8 @@
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
+#define VRAM_CAPABILITY                         _MMIO(0x138144)
+#define   VRAM_SUPPORTED                        REG_BIT(0)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8d2198e29422..778d10520170 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 struct intel_uncore;
+struct drm_i915_private;
 
 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9b7e93ca1ff9..44ea336e1d51 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8287,6 +8287,51 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
 }
 
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
+{
+	if (!HAS_LMEM_SR(i915))
+		return;
+
+	i915->vram_sr_supported = intel_uncore_read(&i915->uncore,
+						    VRAM_CAPABILITY) & VRAM_SUPPORTED;
+	if (intel_opregion_vram_sr_required(i915))
+		i915->vram_sr_supported = i915->vram_sr_supported &&
+						intel_opregion_bios_supports_vram_sr(i915);
+	drm_dbg(&i915->drm, "VRAM Self Refresh supported:%s\n",
+		str_yes_no(i915->vram_sr_supported));
+}
+
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
+{
+	int ret = 0;
+
+	ret = snb_pcode_write(&i915->uncore,
+			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+			      DG1_PCODE_D3_VRAM_SR) |
+			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */
+
+	return ret;
+}
+
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	int ret = 0;
+
+	if (!i915->vram_sr_supported)
+		return ret;
+
+	if (enable)
+		ret = intel_pcode_enable_vram_sr(i915);
+
+	if (ret)
+		return ret;
+
+	intel_opregion_vram_sr(i915, enable);
+
+	return ret;
+}
+
 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
 {
 	struct intel_dbuf_state *dbuf_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 945503ae493e..ffab65431c6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
-- 
2.26.2

[Intel-gfx] [PATCH v3 7/9] Drm/i915/rpm: Enable D3Cold VRAM SR Support

[Anshuman Gupta]

Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.

i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with additional power cost which required to retain
the lmem.

Adding intel_runtime_idle (runtime_idle callback) to enable
VRAM_SR, it will be used for policy to choose
between D3Cold-off vs D3Cold-VRAM_SR.

Since we have introduced i915 runtime_idle callback.
It need to be warranted that Runtime PM Core invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.

TODO: GT and GuC Interface state save/restore on VRAM_SR entry/exit.

v2:
- Remove drm_dbg("VRAM Self Refresh enabled"). [Jani]

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 1bc6227c0287..7357639456b5 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1573,6 +1573,31 @@ static int i915_pm_restore(struct device *kdev)
 	return i915_pm_resume(kdev);
 }
 
+static int intel_runtime_idle(struct device *kdev)
+{
+	struct drm_i915_private *i915 = kdev_to_i915(kdev);
+	int ret = 1;
+
+	if (!HAS_LMEM_SR(i915)) {
+		/*TODO: Prepare for D3Cold-Off */
+		goto out;
+	}
+
+	disable_rpm_wakeref_asserts(&i915->runtime_pm);
+
+	ret = intel_pm_vram_sr(i915, true);
+	if (!ret)
+		ret = 1;
+
+	enable_rpm_wakeref_asserts(&i915->runtime_pm);
+
+out:
+	pm_runtime_mark_last_busy(kdev);
+	pm_runtime_autosuspend(kdev);
+
+	return ret;
+}
+
 static int intel_runtime_suspend(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
@@ -1758,6 +1783,7 @@ const struct dev_pm_ops i915_pm_ops = {
 	.restore = i915_pm_restore,
 
 	/* S0ix (via runtime suspend) event handlers */
+	.runtime_idle = intel_runtime_idle,
 	.runtime_suspend = intel_runtime_suspend,
 	.runtime_resume = intel_runtime_resume,
 };
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6ed5786bcd29..4dade7e8a795 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm,
 
 	intel_runtime_pm_release(rpm, wakelock);
 
-	pm_runtime_mark_last_busy(kdev);
-	pm_runtime_put_autosuspend(kdev);
+	pm_runtime_put(kdev);
 }
 
 /**
-- 
2.26.2

[Intel-gfx] [PATCH v3 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Anshuman Gupta]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.

v2:
- Use forward decalaration instead of heder file. [Jani]

Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8da3314bb6bf..48f509810f66 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -93,6 +93,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
 	GEM_BUG_ON(!HAS_REGION(i915, id));
 	GEM_BUG_ON(i915->mm.regions[id]);
 	i915->mm.regions[id] = mem;
+	gt->lmem = mem;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index df708802889d..37e7716a76ca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -34,6 +34,7 @@ struct drm_i915_private;
 struct i915_ggtt;
 struct intel_engine_cs;
 struct intel_uncore;
+struct intel_memory_region;
 
 struct intel_mmio_range {
 	u32 start;
@@ -202,6 +203,8 @@ struct intel_gt {
 	 */
 	phys_addr_t phys_addr;
 
+	struct intel_memory_region *lmem;
+
 	struct intel_gt_info {
 		unsigned int id;
 
-- 
2.26.2

[Intel-gfx] [PATCH v3 9/9] drm/i915/rpm: d3cold Policy

[Anshuman Gupta]

Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off. if platform does not supports vram_sr
feature then fall back to d3hot by disabling d3cold to
avoid the rpm suspend/resume latency.
Extend the d3cold_sr_lmem_threshold modparam to debugfs
i915_params so that, it can be used by igt test.

If gfx root port is not capable of sending PME from d3cold
or doesn't have _PR3 power resources then only d3hot state
can be supported.

Adding intel_pm_prepare_targeted_d3_state() to choose the
correct target d3 state and cache it to intel_runtime_pm
structure, it can be used in rpm suspend/resume callback
accordingly.

FIXME: Eviction of lmem objects in case of D3Cold off is wip.

v2:
- Proivded abstraction to prepare the target d3 state. [Jani]

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c      | 11 ++----
 drivers/gpu/drm/i915/i915_params.c      |  4 ++
 drivers/gpu/drm/i915/i915_params.h      |  1 +
 drivers/gpu/drm/i915/intel_pm.c         | 50 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.h |  7 ++++
 6 files changed, 67 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 7357639456b5..bbc141acd7f3 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1578,20 +1578,14 @@ static int intel_runtime_idle(struct device *kdev)
 	struct drm_i915_private *i915 = kdev_to_i915(kdev);
 	int ret = 1;
 
-	if (!HAS_LMEM_SR(i915)) {
-		/*TODO: Prepare for D3Cold-Off */
-		goto out;
-	}
-
 	disable_rpm_wakeref_asserts(&i915->runtime_pm);
 
-	ret = intel_pm_vram_sr(i915, true);
+	ret = intel_pm_prepare_targeted_d3_state(i915);
 	if (!ret)
 		ret = 1;
 
 	enable_rpm_wakeref_asserts(&i915->runtime_pm);
 
-out:
 	pm_runtime_mark_last_busy(kdev);
 	pm_runtime_autosuspend(kdev);
 
@@ -1703,6 +1697,9 @@ static int intel_runtime_resume(struct device *kdev)
 	drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
 	disable_rpm_wakeref_asserts(rpm);
 
+	if (rpm->d3_state == INTEL_D3COLD_VRAM_SR)
+		ret = intel_pm_vram_sr(dev_priv, false);
+
 	intel_opregion_notify_adapter(dev_priv, PCI_D0);
 	rpm->suspended = false;
 	pci_d3cold_enable(pdev);
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..29ed3992d1ed 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
 	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
 #endif
 
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0600,
+	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "
+	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
+
 #if CONFIG_DRM_I915_REQUEST_TIMEOUT
 i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 			"Default request/fence/batch buffer expiration timeout.");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..a6be36001ded 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
 	param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
 	param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
 	param(unsigned int, lmem_size, 0, 0400) \
+	param(int, d3cold_sr_lmem_threshold, 300, 0600) \
 	/* leave bools at the end to not create holes */ \
 	param(bool, enable_hangcheck, true, 0600) \
 	param(bool, load_detect_test, false, 0600) \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 44ea336e1d51..72d9a4b3622a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8332,6 +8332,56 @@ int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
 	return ret;
 }
 
+int intel_pm_prepare_targeted_d3_state(struct drm_i915_private *i915)
+{
+	struct intel_runtime_pm *rpm = &i915->runtime_pm;
+	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+	u64 lmem_total, lmem_avail, lmem_used;
+	struct pci_dev *root_pdev;
+	int ret = 0;
+
+	/* igfx will return from here */
+	root_pdev = pcie_find_root_port(pdev);
+	if (!root_pdev)
+		return ret;
+
+	/* D3Cold requires PME capability and _PR3 power resource */
+	if (!pci_pme_capable(root_pdev, PCI_D3cold) || !pci_pr3_present(root_pdev))
+		return ret;
+
+	lmem_total = to_gt(i915)->lmem->total;
+	lmem_avail = to_gt(i915)->lmem->avail;
+	lmem_used = lmem_total - lmem_avail;
+
+	if (lmem_used < i915->params.d3cold_sr_lmem_threshold  * 1024 * 1024) {
+		ret = intel_pm_vram_sr(i915, false);
+		if (!ret) {
+			rpm->d3_state = INTEL_D3COLD_OFF;
+			drm_dbg(&i915->drm, "Prepared for D3Cold off\n");
+		} else {
+			rpm->d3_state = INTEL_D3HOT;
+		}
+	} else if (!HAS_LMEM_SR(i915)) {
+		/* Disable D3Cold to reduce the eviction latency */
+		rpm->d3_state = INTEL_D3HOT;
+	} else {
+		ret = intel_pm_vram_sr(i915, true);
+		if (!ret) {
+			rpm->d3_state = INTEL_D3COLD_VRAM_SR;
+			drm_dbg(&i915->drm, "Prepared for VRAM Self Refresh\n");
+		} else {
+			rpm->d3_state = INTEL_D3HOT;
+		}
+	}
+
+	if (rpm->d3_state == INTEL_D3HOT)
+		pci_d3cold_disable(root_pdev);
+	else
+		pci_d3cold_enable(root_pdev);
+
+	return ret;
+}
+
 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
 {
 	struct intel_dbuf_state *dbuf_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index ffab65431c6c..6644271e6c42 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -33,6 +33,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
 void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
 int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
+int intel_pm_prepare_targeted_d3_state(struct drm_i915_private *i915);
 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index d9160e3ff4af..49bcd2366609 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -22,6 +22,12 @@ enum i915_drm_suspend_mode {
 	I915_DRM_SUSPEND_HIBERNATE,
 };
 
+enum intel_gfx_d3_state {
+	INTEL_D3HOT,
+	INTEL_D3COLD_OFF,
+	INTEL_D3COLD_VRAM_SR,
+};
+
 /*
  * This struct helps tracking the state needed for runtime PM, which puts the
  * device in PCI D3 state. Notice that when this happens, nothing on the
@@ -52,6 +58,7 @@ struct intel_runtime_pm {
 	bool suspended;
 	bool irqs_enabled;
 	bool no_wakeref_tracking;
+	enum intel_gfx_d3_state d3_state;
 
 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 	/*
-- 
2.26.2

[Intel-gfx] ✗ Fi.CI.BUILD: failure for DG2 VRAM_SR Support (rev4)

[Patchwork]

== Series Details ==

Series: DG2 VRAM_SR Support (rev4)
URL   : https://patchwork.freedesktop.org/series/104128/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND objtool
  CHK     include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/intel_pm.o
drivers/gpu/drm/i915/intel_pm.c:8304:5: error: no previous prototype for ‘intel_pcode_enable_vram_sr’ [-Werror=missing-prototypes]
 int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
     ^~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:249: recipe for target 'drivers/gpu/drm/i915/intel_pm.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_pm.o] Error 1
scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:466: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:466: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1843: recipe for target 'drivers' failed
make: *** [drivers] Error 2