From: Rob Herring <robh@kernel.org>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org,
Xiubo.Lee@gmail.com, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, lgirdwood@gmail.com,
robh+dt@kernel.org, tiwai@suse.com, nicoleotsuka@gmail.com,
broonie@kernel.org, festevam@gmail.com, krzk+dt@kernel.org,
shengjiu.wang@gmail.com
Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
Date: Fri, 1 Jul 2022 14:54:44 -0600 [thread overview]
Message-ID: <20220701205444.GA1511232-robh@kernel.org> (raw)
In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com>
On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org,
Xiubo.Lee@gmail.com, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, lgirdwood@gmail.com,
robh+dt@kernel.org, tiwai@suse.com, nicoleotsuka@gmail.com,
broonie@kernel.org, festevam@gmail.com, krzk+dt@kernel.org,
perex@perex.cz, shengjiu.wang@gmail.com
Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
Date: Fri, 1 Jul 2022 14:54:44 -0600 [thread overview]
Message-ID: <20220701205444.GA1511232-robh@kernel.org> (raw)
In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com>
On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Shengjiu Wang <shengjiu.wang@nxp.com>
Cc: Xiubo.Lee@gmail.com, nicoleotsuka@gmail.com,
shengjiu.wang@gmail.com, linux-kernel@vger.kernel.org,
lgirdwood@gmail.com, tiwai@suse.com, devicetree@vger.kernel.org,
krzk+dt@kernel.org, perex@perex.cz,
linuxppc-dev@lists.ozlabs.org, festevam@gmail.com,
alsa-devel@alsa-project.org, broonie@kernel.org,
robh+dt@kernel.org
Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
Date: Fri, 1 Jul 2022 14:54:44 -0600 [thread overview]
Message-ID: <20220701205444.GA1511232-robh@kernel.org> (raw)
In-Reply-To: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com>
On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2022-07-01 20:55 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-01 9:32 [PATCH v2 0/6] Add support of two Audio PLL source Shengjiu Wang
2022-07-01 9:32 ` [PATCH v2 1/6] ASoC: fsl_utils: Add function to handle PLL clock source Shengjiu Wang
2022-07-01 9:32 ` [PATCH v2 2/6] ASoC: fsl_spdif: Add support for PLL switch at runtime Shengjiu Wang
2022-07-01 9:32 ` [PATCH v2 3/6] ASoC: fsl_micfil: " Shengjiu Wang
2022-07-01 9:32 ` [PATCH v2 4/6] ASoC: fsl_sai: " Shengjiu Wang
2022-07-01 9:32 ` [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Shengjiu Wang
2022-07-01 20:54 ` Rob Herring [this message]
2022-07-01 20:54 ` Rob Herring
2022-07-01 20:54 ` Rob Herring
2022-07-01 9:32 ` [PATCH v2 6/6] ASoC: dt-bindings: fsl-sai: " Shengjiu Wang
2022-07-01 20:54 ` Rob Herring
2022-07-01 20:54 ` Rob Herring
2022-07-01 20:54 ` Rob Herring
2022-07-06 11:07 ` [PATCH v2 0/6] Add support of two Audio PLL source Mark Brown
2022-07-06 11:07 ` Mark Brown
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