From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: <ira.weiny@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Lukas Wunner <lukas@wunner.de>,
Alison Schofield <alison.schofield@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Ben Widawsky" <bwidawsk@kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: Re: [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices
Date: Tue, 19 Jul 2022 17:38:20 +0100 [thread overview]
Message-ID: <20220719173820.00004e6e@Huawei.com> (raw)
In-Reply-To: <20220715030424.462963-5-ira.weiny@intel.com>
On Thu, 14 Jul 2022 20:04:21 -0700
ira.weiny@intel.com wrote:
> From: Ira Weiny <ira.weiny@intel.com>
>
> DOE mailbox objects will be needed for various mailbox communications
> with each memory device.
>
> Iterate each DOE mailbox capability and create PCI DOE mailbox objects
> as found.
>
> It is not anticipated that this is the final resting place for the
> iteration of the DOE devices. The support of switch ports will drive
> this code into the PCIe side. In this imagined architecture the CXL
> port driver would then query into the PCI device for the DOE mailbox
> array.
>
> For now creating the mailboxes in the CXL port is good enough for the
> endpoints. Later PCIe ports will need to support this to support switch
> ports more generically.
>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Davidlohr Bueso <dave@stgolabs.net>
> Cc: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2022-07-19 16:38 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 3:04 [PATCH V14 0/7] CXL: Read CDAT ira.weiny
2022-07-15 3:04 ` [PATCH V14 1/7] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-07-15 3:04 ` [PATCH V14 2/7] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-07-15 3:04 ` [PATCH V14 3/7] PCI/DOE: Add DOE mailbox support functions ira.weiny
2022-07-19 16:35 ` Jonathan Cameron
2022-07-19 19:16 ` Ira Weiny
2022-07-19 19:50 ` Ira Weiny
2022-07-20 11:24 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 4/7] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-07-19 16:38 ` Jonathan Cameron [this message]
2022-07-15 3:04 ` [PATCH V14 5/7] driver-core: Introduce BIN_ATTR_ADMIN_{RO,RW} ira.weiny
2022-07-19 16:39 ` Jonathan Cameron
2022-07-15 3:04 ` [PATCH V14 6/7] cxl/port: Read CDAT table ira.weiny
2022-07-16 3:27 ` Dan Williams
2022-07-19 1:19 ` Dan Williams
2022-07-19 1:55 ` [PATCH v15 " Dan Williams
2022-07-19 16:46 ` Jonathan Cameron
2022-07-19 19:26 ` Dan Williams
2022-07-15 3:04 ` [PATCH V14 7/7] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-07-16 2:26 ` Dan Williams
2022-07-19 16:47 ` Jonathan Cameron
2022-07-19 15:21 ` [PATCH V14 0/7] CXL: Read CDAT Jonathan Cameron
2022-07-19 19:23 ` Dan Williams
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