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From: Anup Patel <apatel@ventanamicro.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Samuel Holland <samuel@sholland.org>,
	Anup Patel <anup@brainfault.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu
Date: Wed, 27 Jul 2022 17:13:01 +0530	[thread overview]
Message-ID: <20220727114302.302201-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220727114302.302201-1-apatel@ventanamicro.com>

We add an optional DT property riscv,timer-can-wake-cpu which if present
in CPU DT node then CPU timer is always powered-on and never loses context.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b60b64b4113a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -78,6 +78,12 @@ properties:
       - rv64imac
       - rv64imafdc
 
+  riscv,timer-can-wake-cpu:
+    type: boolean
+    description:
+      If present, the timer interrupt can wake up the CPU from
+      suspend/idle state.
+
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.34.1


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WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Samuel Holland <samuel@sholland.org>,
	Anup Patel <anup@brainfault.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu
Date: Wed, 27 Jul 2022 17:13:01 +0530	[thread overview]
Message-ID: <20220727114302.302201-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20220727114302.302201-1-apatel@ventanamicro.com>

We add an optional DT property riscv,timer-can-wake-cpu which if present
in CPU DT node then CPU timer is always powered-on and never loses context.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..b60b64b4113a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -78,6 +78,12 @@ properties:
       - rv64imac
       - rv64imafdc
 
+  riscv,timer-can-wake-cpu:
+    type: boolean
+    description:
+      If present, the timer interrupt can wake up the CPU from
+      suspend/idle state.
+
   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
   timebase-frequency: false
 
-- 
2.34.1


  reply	other threads:[~2022-07-27 11:44 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-27 11:43 [PATCH v2 0/2] Improve CLOCK_EVT_FEAT_C3STOP feature setting Anup Patel
2022-07-27 11:43 ` Anup Patel
2022-07-27 11:43 ` Anup Patel [this message]
2022-07-27 11:43   ` [PATCH v2 1/2] dt-bindings: riscv: Add optional DT property riscv,timer-can-wake-cpu Anup Patel
2022-07-27 12:07   ` Krzysztof Kozlowski
2022-07-27 12:07     ` Krzysztof Kozlowski
2022-07-27 12:21     ` Anup Patel
2022-07-27 12:21       ` Anup Patel
2022-07-27 12:35       ` Krzysztof Kozlowski
2022-07-27 12:35         ` Krzysztof Kozlowski
2022-07-27 13:34         ` Anup Patel
2022-07-27 13:34           ` Anup Patel
2022-11-22 14:57           ` Conor Dooley
2022-11-22 14:57             ` Conor Dooley
2022-11-23  5:43             ` Samuel Holland
2022-11-23  5:43               ` Samuel Holland
2022-11-23 11:49               ` Conor Dooley
2022-11-23 11:49                 ` Conor Dooley
2022-11-23 13:46             ` Conor Dooley
2022-11-23 13:46               ` Conor Dooley
2022-11-23 15:46               ` Anup Patel
2022-11-23 15:46                 ` Anup Patel
2022-11-23 17:59                 ` Conor Dooley
2022-11-23 17:59                   ` Conor Dooley
2022-07-27 12:45     ` Sudeep Holla
2022-07-27 12:45       ` Sudeep Holla
2022-07-27 13:19       ` Anup Patel
2022-07-27 13:19         ` Anup Patel
2022-07-27 13:45       ` Anup Patel
2022-07-27 13:45         ` Anup Patel
2022-07-27 15:26         ` Sudeep Holla
2022-07-27 15:26           ` Sudeep Holla
2022-07-27 12:18   ` Sudeep Holla
2022-07-27 12:18     ` Sudeep Holla
2022-07-27 12:29     ` Anup Patel
2022-07-27 12:29       ` Anup Patel
2022-07-27 11:43 ` [PATCH v2 2/2] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT property Anup Patel
2022-07-27 11:43   ` Anup Patel

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