* [RESEND PATCH v3 0/2] MediaTek Kompanio 1200 MT8195 - DisplayPort clocks fixes
@ 2022-08-16 19:32 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw)
To: Michael Turquette
Cc: Bo-Chen Chen, Nícolas F. R. A. Prado,
AngeloGioacchino Del Regno, Chen-Yu Tsai, Matthias Brugger,
Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk,
linux-kernel, linux-mediatek
This series fixes the two DPINTF clocks to propagate rate change
requests to their own parent (and also fixes vdo1_dpintf's parent name).
This is needed in order to stay clean in the DisplayPort driver and
avoid adding (now useless) custom handling of clocks reparenting based
on the wanted final clock rate.
Original v3: https://lore.kernel.org/all/20220617111248.90505-1-angelogioacchino.delregno@collabora.com/
Changes in v3:
- Fixed tags ordering.
AngeloGioacchino Del Regno (2):
clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's
parent
clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's
parent
drivers/clk/mediatek/clk-mt8195-vdo0.c | 7 ++++++-
drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++-
2 files changed, 11 insertions(+), 2 deletions(-)
--
2.37.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [RESEND PATCH v3 0/2] MediaTek Kompanio 1200 MT8195 - DisplayPort clocks fixes @ 2022-08-16 19:32 ` Nícolas F. R. A. Prado 0 siblings, 0 replies; 10+ messages in thread From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw) To: Michael Turquette Cc: Bo-Chen Chen, Nícolas F. R. A. Prado, AngeloGioacchino Del Regno, Chen-Yu Tsai, Matthias Brugger, Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek This series fixes the two DPINTF clocks to propagate rate change requests to their own parent (and also fixes vdo1_dpintf's parent name). This is needed in order to stay clean in the DisplayPort driver and avoid adding (now useless) custom handling of clocks reparenting based on the wanted final clock rate. Original v3: https://lore.kernel.org/all/20220617111248.90505-1-angelogioacchino.delregno@collabora.com/ Changes in v3: - Fixed tags ordering. AngeloGioacchino Del Regno (2): clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent drivers/clk/mediatek/clk-mt8195-vdo0.c | 7 ++++++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++- 2 files changed, 11 insertions(+), 2 deletions(-) -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent 2022-08-16 19:32 ` Nícolas F. R. A. Prado @ 2022-08-16 19:32 ` Nícolas F. R. A. Prado -1 siblings, 0 replies; 10+ messages in thread From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw) To: Michael Turquette Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF clock: this is required to trigger clock source selection on CLK_TOP_EDP, while avoiding to manage the enablement of the former separately from the latter in the displayport driver. Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/clk/mediatek/clk-mt8195-vdo0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index 261a7f76dd3c..07b46bfd5040 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -37,6 +37,10 @@ static const struct mtk_gate_regs vdo0_2_cg_regs = { #define GATE_VDO0_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + static const struct mtk_gate vdo0_clks[] = { /* VDO0_0 */ GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), @@ -85,7 +89,8 @@ static const struct mtk_gate vdo0_clks[] = { /* VDO0_2 */ GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), - GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16), + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", + "top_edp", 16, CLK_SET_RATE_PARENT), }; static int clk_mt8195_vdo0_probe(struct platform_device *pdev) -- 2.37.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent @ 2022-08-16 19:32 ` Nícolas F. R. A. Prado 0 siblings, 0 replies; 10+ messages in thread From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw) To: Michael Turquette Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF clock: this is required to trigger clock source selection on CLK_TOP_EDP, while avoiding to manage the enablement of the former separately from the latter in the displayport driver. Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/clk/mediatek/clk-mt8195-vdo0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index 261a7f76dd3c..07b46bfd5040 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -37,6 +37,10 @@ static const struct mtk_gate_regs vdo0_2_cg_regs = { #define GATE_VDO0_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + static const struct mtk_gate vdo0_clks[] = { /* VDO0_0 */ GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "top_vpp", 0), @@ -85,7 +89,8 @@ static const struct mtk_gate vdo0_clks[] = { /* VDO0_2 */ GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "top_dsi_occ", 0), GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "top_dsi_occ", 8), - GATE_VDO0_2(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "top_edp", 16), + GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", + "top_edp", 16, CLK_SET_RATE_PARENT), }; static int clk_mt8195_vdo0_probe(struct platform_device *pdev) -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent 2022-08-16 19:32 ` Nícolas F. R. A. Prado @ 2022-08-31 17:51 ` Stephen Boyd -1 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2022-08-31 17:51 UTC (permalink / raw) To: Michael Turquette, Nícolas F. R. A. Prado Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:55) > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF > clock: this is required to trigger clock source selection on > CLK_TOP_EDP, while avoiding to manage the enablement of the former > separately from the latter in the displayport driver. > > Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > --- Applied to clk-next ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent @ 2022-08-31 17:51 ` Stephen Boyd 0 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2022-08-31 17:51 UTC (permalink / raw) To: Michael Turquette, Nícolas F. R. A. Prado Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:55) > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF > clock: this is required to trigger clock source selection on > CLK_TOP_EDP, while avoiding to manage the enablement of the former > separately from the latter in the displayport driver. > > Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent 2022-08-16 19:32 ` Nícolas F. R. A. Prado @ 2022-08-16 19:32 ` Nícolas F. R. A. Prado -1 siblings, 0 replies; 10+ messages in thread From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw) To: Michael Turquette Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 3378487d2c90..d54d7726d186 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -43,6 +43,10 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { #define GATE_VDO1_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -99,7 +103,7 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1), GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9), - GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16), + GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8), -- 2.37.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent @ 2022-08-16 19:32 ` Nícolas F. R. A. Prado 0 siblings, 0 replies; 10+ messages in thread From: Nícolas F. R. A. Prado @ 2022-08-16 19:32 UTC (permalink / raw) To: Michael Turquette Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, Stephen Boyd, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) and also fix its parent clock name as it has to be "top_dp" for two reasons: - This is its real parent! - Likewise to eDP/VDO0 counterpart, we need clock source selection on CLK_TOP_DP. Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> --- drivers/clk/mediatek/clk-mt8195-vdo1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 3378487d2c90..d54d7726d186 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -43,6 +43,10 @@ static const struct mtk_gate_regs vdo1_3_cg_regs = { #define GATE_VDO1_2(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, _flags) + #define GATE_VDO1_3(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) @@ -99,7 +103,7 @@ static const struct mtk_gate vdo1_clks[] = { GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0", "top_vpp", 1), GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1", "top_vpp", 8), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1", "top_vpp", 9), - GATE_VDO1_2(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_vpp", 16), + GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf", "top_dp", 16, CLK_SET_RATE_PARENT), GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf", "top_vpp", 17), /* VDO1_3 */ GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow", "clk26m", 8), -- 2.37.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent 2022-08-16 19:32 ` Nícolas F. R. A. Prado @ 2022-08-31 17:51 ` Stephen Boyd -1 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2022-08-31 17:51 UTC (permalink / raw) To: Michael Turquette, Nícolas F. R. A. Prado Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:56) > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), > add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) > and also fix its parent clock name as it has to be "top_dp" for two > reasons: > - This is its real parent! > - Likewise to eDP/VDO0 counterpart, we need clock source > selection on CLK_TOP_DP. > > Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- Applied to clk-next ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent @ 2022-08-31 17:51 ` Stephen Boyd 0 siblings, 0 replies; 10+ messages in thread From: Stephen Boyd @ 2022-08-31 17:51 UTC (permalink / raw) To: Michael Turquette, Nícolas F. R. A. Prado Cc: Bo-Chen Chen, AngeloGioacchino Del Regno, Nícolas F . R . A . Prado, Chen-Yu Tsai, Matthias Brugger, Miles Chen, linux-arm-kernel, linux-clk, linux-kernel, linux-mediatek Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:56) > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > > Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP), > add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP) > and also fix its parent clock name as it has to be "top_dp" for two > reasons: > - This is its real parent! > - Likewise to eDP/VDO0 counterpart, we need clock source > selection on CLK_TOP_DP. > > Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support") > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-08-31 17:53 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-08-16 19:32 [RESEND PATCH v3 0/2] MediaTek Kompanio 1200 MT8195 - DisplayPort clocks fixes Nícolas F. R. A. Prado 2022-08-16 19:32 ` Nícolas F. R. A. Prado 2022-08-16 19:32 ` [RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent Nícolas F. R. A. Prado 2022-08-16 19:32 ` Nícolas F. R. A. Prado 2022-08-31 17:51 ` Stephen Boyd 2022-08-31 17:51 ` Stephen Boyd 2022-08-16 19:32 ` [RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent Nícolas F. R. A. Prado 2022-08-16 19:32 ` Nícolas F. R. A. Prado 2022-08-31 17:51 ` Stephen Boyd 2022-08-31 17:51 ` Stephen Boyd
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