From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v5 0/4] Add PMEM support for RISC-V
Date: Thu, 20 Oct 2022 13:28:42 +0530 [thread overview]
Message-ID: <20221020075846.305576-1-apatel@ventanamicro.com> (raw)
The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.
First two patches are fixes and remaining two patches add the required
PMEM support for Linux RISC-V.
These patches can also be found in riscv_pmem_v5 branch at:
https://github.com/avpatel/linux.git
Changes since v4:
- Simplify PATCH2 by implementing RISC-V specific arch_memremap_wb()
Changes since v3:
- Pickup correct version of Drew's patch as PATCH1
Changes since v2:
- Rebased on Linux-6.1-rc1
- Replaced PATCH1 with the patch proposed by Drew
Changes since v1:
- Fix error reported by test bot
https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/
Andrew Jones (1):
RISC-V: Fix compilation without RISCV_ISA_ZICBOM
Anup Patel (3):
RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
RISC-V: Implement arch specific PMEM APIs
RISC-V: Enable PMEM drivers
arch/riscv/Kconfig | 1 +
arch/riscv/configs/defconfig | 1 +
arch/riscv/include/asm/cacheflush.h | 8 ------
arch/riscv/include/asm/io.h | 5 ++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++
arch/riscv/mm/dma-noncoherent.c | 41 -----------------------------
arch/riscv/mm/pmem.c | 21 +++++++++++++++
8 files changed, 67 insertions(+), 49 deletions(-)
create mode 100644 arch/riscv/mm/pmem.c
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>
Cc: Atish Patra <atishp@atishpatra.org>,
Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v5 0/4] Add PMEM support for RISC-V
Date: Thu, 20 Oct 2022 13:28:42 +0530 [thread overview]
Message-ID: <20221020075846.305576-1-apatel@ventanamicro.com> (raw)
The Linux NVDIMM PEM drivers require arch support to map and access the
persistent memory device. This series adds RISC-V PMEM support using
recently added Svpbmt and Zicbom support.
First two patches are fixes and remaining two patches add the required
PMEM support for Linux RISC-V.
These patches can also be found in riscv_pmem_v5 branch at:
https://github.com/avpatel/linux.git
Changes since v4:
- Simplify PATCH2 by implementing RISC-V specific arch_memremap_wb()
Changes since v3:
- Pickup correct version of Drew's patch as PATCH1
Changes since v2:
- Rebased on Linux-6.1-rc1
- Replaced PATCH1 with the patch proposed by Drew
Changes since v1:
- Fix error reported by test bot
https://lore.kernel.org/all/202208272028.IwrNZ0Ur-lkp@intel.com/
Andrew Jones (1):
RISC-V: Fix compilation without RISCV_ISA_ZICBOM
Anup Patel (3):
RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
RISC-V: Implement arch specific PMEM APIs
RISC-V: Enable PMEM drivers
arch/riscv/Kconfig | 1 +
arch/riscv/configs/defconfig | 1 +
arch/riscv/include/asm/cacheflush.h | 8 ------
arch/riscv/include/asm/io.h | 5 ++++
arch/riscv/mm/Makefile | 1 +
arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++
arch/riscv/mm/dma-noncoherent.c | 41 -----------------------------
arch/riscv/mm/pmem.c | 21 +++++++++++++++
8 files changed, 67 insertions(+), 49 deletions(-)
create mode 100644 arch/riscv/mm/pmem.c
--
2.34.1
next reply other threads:[~2022-10-20 7:59 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 7:58 Anup Patel [this message]
2022-10-20 7:58 ` [PATCH v5 0/4] Add PMEM support for RISC-V Anup Patel
2022-10-20 7:58 ` [PATCH v5 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Anup Patel
2022-10-20 7:58 ` Anup Patel
2022-10-21 6:48 ` Anup Patel
2022-10-21 6:48 ` Anup Patel
2022-10-20 7:58 ` [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Anup Patel
2022-10-20 7:58 ` Anup Patel
2022-10-24 19:54 ` Conor Dooley
2022-10-24 19:54 ` Conor Dooley
2022-10-20 7:58 ` [PATCH v5 3/4] RISC-V: Implement arch specific PMEM APIs Anup Patel
2022-10-20 7:58 ` Anup Patel
2022-10-24 19:52 ` Conor Dooley
2022-10-24 19:52 ` Conor Dooley
2022-11-14 9:02 ` Anup Patel
2022-11-14 9:02 ` Anup Patel
2022-10-20 7:58 ` [PATCH v5 4/4] RISC-V: Enable PMEM drivers Anup Patel
2022-10-20 7:58 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20221020075846.305576-1-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=arnd@arndb.de \
--cc=atishp@atishpatra.org \
--cc=heiko@sntech.de \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.