[PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set

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From: Marc Zyngier <maz@kernel.org>
To: <kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
	kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: Will Deacon <will@kernel.org>
Subject: [PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set
Date: Thu, 20 Oct 2022 10:07:16 +0100	[thread overview]
Message-ID: <20221020090727.3669908-7-maz@kernel.org> (raw)
In-Reply-To: <20221020090727.3669908-1-maz@kernel.org>

When HCR_EL2.E2H is set, the CPTR_EL2 register takes the CPACR_EL1
format. Yes, this is good fun.

Hack the bits of startup code that assume E2H=0 while setting up
CPTR_EL2 to make them grok the CPTR_EL1 format.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/el2_setup.h | 11 +++++++++--
 arch/arm64/kernel/hyp-stub.S       | 11 +++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index fa1045f709bb..605ff1a482db 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -129,8 +129,15 @@
 .endm
 
 /* Coprocessor traps */
-.macro __init_el2_nvhe_cptr
+.macro __init_el2_cptr
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .LnVHE_\@
+	mov	x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)
+	b	.Lset_cptr_\@
+.LnVHE_\@:
 	mov	x0, #0x33ff
+.Lset_cptr_\@:
 	msr	cptr_el2, x0			// Disable copro. traps to EL2
 .endm
 
@@ -196,7 +203,7 @@
 	__init_el2_gicv3
 	__init_el2_hstr
 	__init_el2_nvhe_idregs
-	__init_el2_nvhe_cptr
+	__init_el2_cptr
 	__init_el2_fgt
 	__init_el2_nvhe_prepare_eret
 .endm
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 0601cc9592bd..7d2f24ae8c98 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -102,7 +102,18 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 
 .Linit_sve:	/* SVE register access */
 	mrs	x0, cptr_el2			// Disable SVE traps
+
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .Lcptr_nvhe
+
+	// VHE case
+	orr	x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
+	b	.Lset_cptr
+
+.Lcptr_nvhe: // nVHE case
 	bic	x0, x0, #CPTR_EL2_TZ
+.Lset_cptr:
 	msr	cptr_el2, x0
 	isb
 	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector
-- 
2.34.1

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kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)

From: Marc Zyngier <maz@kernel.org>
To: <kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
	kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Quentin Perret <qperret@google.com>,
	Will Deacon <will@kernel.org>, Fuad Tabba <tabba@google.com>
Subject: [PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set
Date: Thu, 20 Oct 2022 10:07:16 +0100	[thread overview]
Message-ID: <20221020090727.3669908-7-maz@kernel.org> (raw)
Message-ID: <20221020090716.kT1Zu_Es1388SHuaKr7DeR2WsJPGz6B1EkwranX4eeY@z> (raw)
In-Reply-To: <20221020090727.3669908-1-maz@kernel.org>

When HCR_EL2.E2H is set, the CPTR_EL2 register takes the CPACR_EL1
format. Yes, this is good fun.

Hack the bits of startup code that assume E2H=0 while setting up
CPTR_EL2 to make them grok the CPTR_EL1 format.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/el2_setup.h | 11 +++++++++--
 arch/arm64/kernel/hyp-stub.S       | 11 +++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index fa1045f709bb..605ff1a482db 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -129,8 +129,15 @@
 .endm
 
 /* Coprocessor traps */
-.macro __init_el2_nvhe_cptr
+.macro __init_el2_cptr
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .LnVHE_\@
+	mov	x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)
+	b	.Lset_cptr_\@
+.LnVHE_\@:
 	mov	x0, #0x33ff
+.Lset_cptr_\@:
 	msr	cptr_el2, x0			// Disable copro. traps to EL2
 .endm
 
@@ -196,7 +203,7 @@
 	__init_el2_gicv3
 	__init_el2_hstr
 	__init_el2_nvhe_idregs
-	__init_el2_nvhe_cptr
+	__init_el2_cptr
 	__init_el2_fgt
 	__init_el2_nvhe_prepare_eret
 .endm
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 0601cc9592bd..7d2f24ae8c98 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -102,7 +102,18 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 
 .Linit_sve:	/* SVE register access */
 	mrs	x0, cptr_el2			// Disable SVE traps
+
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .Lcptr_nvhe
+
+	// VHE case
+	orr	x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
+	b	.Lset_cptr
+
+.Lcptr_nvhe: // nVHE case
 	bic	x0, x0, #CPTR_EL2_TZ
+.Lset_cptr:
 	msr	cptr_el2, x0
 	isb
 	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector
-- 
2.34.1

WARNING: multiple messages have this Message-ID (diff)

From: Marc Zyngier <maz@kernel.org>
To: <kvmarm@lists.cs.columbia.edu>, <kvmarm@lists.linux.dev>,
	kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Cc: James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Quentin Perret <qperret@google.com>,
	Will Deacon <will@kernel.org>, Fuad Tabba <tabba@google.com>
Subject: [PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set
Date: Thu, 20 Oct 2022 10:07:16 +0100	[thread overview]
Message-ID: <20221020090727.3669908-7-maz@kernel.org> (raw)
In-Reply-To: <20221020090727.3669908-1-maz@kernel.org>

When HCR_EL2.E2H is set, the CPTR_EL2 register takes the CPACR_EL1
format. Yes, this is good fun.

Hack the bits of startup code that assume E2H=0 while setting up
CPTR_EL2 to make them grok the CPTR_EL1 format.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/el2_setup.h | 11 +++++++++--
 arch/arm64/kernel/hyp-stub.S       | 11 +++++++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index fa1045f709bb..605ff1a482db 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -129,8 +129,15 @@
 .endm
 
 /* Coprocessor traps */
-.macro __init_el2_nvhe_cptr
+.macro __init_el2_cptr
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .LnVHE_\@
+	mov	x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN)
+	b	.Lset_cptr_\@
+.LnVHE_\@:
 	mov	x0, #0x33ff
+.Lset_cptr_\@:
 	msr	cptr_el2, x0			// Disable copro. traps to EL2
 .endm
 
@@ -196,7 +203,7 @@
 	__init_el2_gicv3
 	__init_el2_hstr
 	__init_el2_nvhe_idregs
-	__init_el2_nvhe_cptr
+	__init_el2_cptr
 	__init_el2_fgt
 	__init_el2_nvhe_prepare_eret
 .endm
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 0601cc9592bd..7d2f24ae8c98 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -102,7 +102,18 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 
 .Linit_sve:	/* SVE register access */
 	mrs	x0, cptr_el2			// Disable SVE traps
+
+	mrs	x1, hcr_el2
+	and	x1, x1, #HCR_E2H
+	cbz	x1, .Lcptr_nvhe
+
+	// VHE case
+	orr	x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
+	b	.Lset_cptr
+
+.Lcptr_nvhe: // nVHE case
 	bic	x0, x0, #CPTR_EL2_TZ
+.Lset_cptr:
 	msr	cptr_el2, x0
 	isb
 	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector
-- 
2.34.1


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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

next prev parent reply	other threads:[~2022-10-20  9:07 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-20  9:07 [PATCH 00/17] KVM: arm64: Allow using VHE in the nVHE hypervisor Marc Zyngier
2022-10-20  9:07 ` Marc Zyngier
2022-10-20  9:07 ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 01/17] arm64: Turn kaslr_feature_override into a generic SW feature override Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 02/17] arm64: Add KVM_HVHE capability and has_hvhe() predicate Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2023-06-01  7:01   ` Oliver Upton
2023-06-01  7:01     ` Oliver Upton
2022-10-20  9:07 ` [PATCH 03/17] arm64: Don't enable VHE for the kernel if OVERRIDE_HVHE is set Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 04/17] arm64: Prevent the use of is_kernel_in_hyp_mode() in hypervisor code Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 05/17] arm64: Allow EL1 physical timer access when running VHE Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` Marc Zyngier [this message]
2022-10-20  9:07   ` [PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 07/17] KVM: arm64: Elide kern_hyp_va() in VHE-specific parts of the hypervisor Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 08/17] KVM: arm64: Remove alternatives from sysreg accessors in VHE hypervisor context Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 09/17] KVM: arm64: Key use of VHE instructions in nVHE code off ARM64_KVM_HVHE Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 10/17] KVM: arm64: Force HCR_EL2.E2H when ARM64_KVM_HVHE is set Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 11/17] KVM: arm64: Disable TTBR1_EL2 when using ARM64_KVM_HVHE Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 12/17] KVM: arm64: Adjust EL2 stage-1 leaf AP bits when ARM64_KVM_HVHE is set Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 13/17] KVM: arm64: Rework CPTR_EL2 programming for HVHE configuration Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 14/17] KVM: arm64: Program the timer traps with VHE layout in hVHE mode Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 15/17] KVM: arm64: Force HCR_E2H in guest context when ARM64_KVM_HVHE is set Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 16/17] arm64: Allow arm64_sw.hvhe on command line Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07 ` [PATCH 17/17] KVM: arm64: Terrible timer hack for M1 with hVHE Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier
2022-10-20  9:07   ` Marc Zyngier

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:fa1045f709b dfblob:605ff1a482d dfblob:0601cc9592b
dfblob:7d2f24ae8c9 dfblob:fa1045f709b dfblob:605ff1a482d
dfblob:0601cc9592b dfblob:7d2f24ae8c9 dfblob:fa1045f709b
dfblob:605ff1a482d dfblob:0601cc9592b dfblob:7d2f24ae8c9 )
 OR (
bs:"[PATCH 06/17] arm64: Use CPACR_EL1 format to set CPTR_EL2 when E2H is set" )
	(help)

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