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From: Shawn Guo <shawnguo@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, marex@denx.de, tharvey@gateworks.com,
	vkoul@kernel.org, bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	alexander.stein@ew.tq-group.com, richard.leitner@linux.dev,
	devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations
Date: Sat, 29 Oct 2022 16:45:14 +0800	[thread overview]
Message-ID: <20221029084514.GT125525@dragon> (raw)
In-Reply-To: <1666590189-1364-1-git-send-email-hongxing.zhu@nxp.com>

On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> i.MX8MP PCIe reference clock.
> 
> The following properties of PHY dts node should be changed accordingly.
>   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
>   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Applied, thanks!

WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, marex@denx.de, tharvey@gateworks.com,
	vkoul@kernel.org, bhelgaas@google.com, lorenzo.pieralisi@arm.com,
	alexander.stein@ew.tq-group.com, richard.leitner@linux.dev,
	devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations
Date: Sat, 29 Oct 2022 16:45:14 +0800	[thread overview]
Message-ID: <20221029084514.GT125525@dragon> (raw)
In-Reply-To: <1666590189-1364-1-git-send-email-hongxing.zhu@nxp.com>

On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> i.MX8MP PCIe reference clock.
> 
> The following properties of PHY dts node should be changed accordingly.
>   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
>   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Applied, thanks!

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  reply	other threads:[~2022-10-29  8:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-24  5:43 [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations Richard Zhu
2022-10-24  5:43 ` Richard Zhu
2022-10-29  8:45 ` Shawn Guo [this message]
2022-10-29  8:45   ` Shawn Guo
2022-11-01  8:44   ` Lucas Stach
2022-11-01  8:44     ` Lucas Stach
2022-11-02  1:45     ` Hongxing Zhu
2022-11-02  1:45       ` Hongxing Zhu
2022-11-15  2:25       ` Hongxing Zhu
2022-11-15  2:25         ` Hongxing Zhu
2022-11-10  7:15     ` Shawn Guo
2022-11-10  7:15       ` Shawn Guo

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