From: Shawn Guo <shawnguo@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
marex@denx.de, tharvey@gateworks.com, vkoul@kernel.org,
bhelgaas@google.com, lorenzo.pieralisi@arm.com,
alexander.stein@ew.tq-group.com, richard.leitner@linux.dev,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations
Date: Thu, 10 Nov 2022 15:15:15 +0800 [thread overview]
Message-ID: <20221110071515.GC125525@dragon> (raw)
In-Reply-To: <ae0fd778eb31416eedb248e2cd4faef576174937.camel@pengutronix.de>
On Tue, Nov 01, 2022 at 09:44:41AM +0100, Lucas Stach wrote:
> Hi Shawn, Richard,
>
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > > i.MX8MP PCIe reference clock.
> > >
> > > The following properties of PHY dts node should be changed accordingly.
> > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Applied, thanks!
>
> Sorry for the late reply, but I'm not really happy with the fact that
> the PLL is now unconditionally enabled, even though it is only needed
> when there is no external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction
> is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
> PHY, but the PLL generated clock, which isn't properly exposed with
> this series.
>
> I'm not happy to see this going in in the current state and if not too
> late would like to ask Shawn to remove it from the tree again.
Removed.
Shawn
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo@kernel.org>
To: Lucas Stach <l.stach@pengutronix.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
marex@denx.de, tharvey@gateworks.com, vkoul@kernel.org,
bhelgaas@google.com, lorenzo.pieralisi@arm.com,
alexander.stein@ew.tq-group.com, richard.leitner@linux.dev,
devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de,
linux-imx@nxp.com
Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations
Date: Thu, 10 Nov 2022 15:15:15 +0800 [thread overview]
Message-ID: <20221110071515.GC125525@dragon> (raw)
In-Reply-To: <ae0fd778eb31416eedb248e2cd4faef576174937.camel@pengutronix.de>
On Tue, Nov 01, 2022 at 09:44:41AM +0100, Lucas Stach wrote:
> Hi Shawn, Richard,
>
> Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> > On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > > i.MX8MP PCIe reference clock.
> > >
> > > The following properties of PHY dts node should be changed accordingly.
> > > - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> > > - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > >
> > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> >
> > Applied, thanks!
>
> Sorry for the late reply, but I'm not really happy with the fact that
> the PLL is now unconditionally enabled, even though it is only needed
> when there is no external reference clock source.
> I fear that this will be hard to correct later on as the DT abstraction
> is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
> PHY, but the PLL generated clock, which isn't properly exposed with
> this series.
>
> I'm not happy to see this going in in the current state and if not too
> late would like to ask Shawn to remove it from the tree again.
Removed.
Shawn
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next prev parent reply other threads:[~2022-11-10 7:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 5:43 [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL configurations Richard Zhu
2022-10-24 5:43 ` Richard Zhu
2022-10-29 8:45 ` Shawn Guo
2022-10-29 8:45 ` Shawn Guo
2022-11-01 8:44 ` Lucas Stach
2022-11-01 8:44 ` Lucas Stach
2022-11-02 1:45 ` Hongxing Zhu
2022-11-02 1:45 ` Hongxing Zhu
2022-11-15 2:25 ` Hongxing Zhu
2022-11-15 2:25 ` Hongxing Zhu
2022-11-10 7:15 ` Shawn Guo [this message]
2022-11-10 7:15 ` Shawn Guo
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